RU1784985C - Device for electronic microcomputer interface and periphery line conjugating - Google Patents

Abstract

The invention relates to computer technology and can be used in multiprocessor computer systems. The aim of the present invention is to expand the functionality of the device by providing the ability to connect peripheral devices to the device that do not match the type of microcomputer trunk. The goal is achieved in that, in a device comprising a control signal switch, a control trigger, a first control signal switch, a control signal amplifier assembly and an element NOT, two control signal switches, a control signal conversion unit, an interrupt processing unit, AND element, AND element, OR element, two control signal receivers and four control signal transmitters. 2 s.p. f-ly, 3 ill.

Description

The invention relates to computer technology and can be used in multiprocessor computer systems.

A device is known for interfacing a central highway with peripheral highways, comprising a switch for information signals, a node for amplifying control signals, an element HE and a control trigger 1.

The disadvantage of this device is the limited functionality associated with the inability to provide direct access to the memory of the microcomputer and the need to connect to the central highway peripheral

Devices having a demobase. the same type with the central one.

Closest to the proposed device is a device for interfacing a microcomputer trunk with a peripheral trunk, comprising an information signal switch, an HE element, a control signal amplifier assembly, a control trigger, a control signal switch, an EXCLUSIVE OR element, and a trunk capture trigger, the first and the second group of information inputs - outputs of the switch information signals are the corresponding groups of inputs and outputs of the device for connecting to the information m buses and highways microcomputer peripherals input and

x |

00

the output of the element is NOT connected by the first and second inputs of the selection of the direction of the switch of information signals, the first and second groups of inputs and outputs of the node of the amplifiers of the control signals are the corresponding groups of inputs and outputs of the device for connecting to the groups of input and output buses of the microcomputer trunk and the groups of input bus lines of peripheral devices, the output of the control trigger is connected to the enable inputs of the switch information signals and node amplifiers of control signals, and the input is set The inputs, the sync input and the information input are the corresponding inputs of the device for connecting to the installation and synchronization buses of the microcomputer trunk exchange and the start input of the device, the first and second groups of inputs and outputs of the control signal switch are the corresponding input and output groups of the device for connecting to control buses of the microcomputer line and the peripheral device line, and the first and second direction selection inputs are connected to the inverse and direct outputs of the capture trigger, respectively trunk, the information input and clock output of which are respectively the inputs of the device for connecting to the request line of the microcomputer line and the bus for confirming the request of the line of peripheral devices, the first input of the AND SCR element is YES or is the input of the device for connecting to the read bus microcomputer trunk data, the inverse output of the trunk capture trigger is connected to the second input of the EXCLUSIVE OR element, the output is connected to the input; item house NOT 2

A disadvantage of this device is its limited functionality due to the fact that k peripheral devices having a trunk of the same type as the central one can be connected to the central line k.

The purpose of the invention is to expand the functionality of the device by providing the ability to connect peripheral devices to the device that are not the same type as the microcomputer trunk.

The goal is achieved that in a device for interfacing a microcomputer trunk with a peripheral trunk, containing a switch for information and address signals and a first switch for control signals, the first and second groups of information inputs and outputs of which are corresponding groups of inputs and outputs of the device for connecting to highways of microcomputers and peripheral devices, a node of control signal amplifiers, the first groups of information inputs and outputs of which are corresponding to by the pins of the inputs and outputs of the device for connecting to the trunk of the microcomputer, and the second groups of its information inputs and outputs are the corresponding groups of inputs and outputs of the device for connecting to the highway of peripheral devices, a control trigger, the information input of which is the start input of the device, the element is NOT, moreover the direct trigger output is connected to the resolution inputs of the first control signal switch, the node of control signal amplifiers and the adder of information-address signals, the first input is selected The direction direction of which is connected to the output of the NOT element, the second and third control signal switches, a control signal conversion unit, an interrupt processing unit, an AND element, an AND-NOT element, an OR element, two control signal receivers, four control transmitters are introduced signals, and the outputs of the AND-NOT and OR elements are connected respectively With the first and second inputs of the AND element, the output connected to the second input of the choice of the direction of the switch information-address signals and the input of the element NOT, information group The inputs and outputs of the second and third control signal switches are the corresponding input / output groups for connecting microcomputers and peripheral devices to the highway, and the information input groups and the output groups, respectively, with the first and second output groups, the second and first groups of information inputs of the control signal conversion unit, the first and second outputs of which are connected respectively to the information inputs of the first and second control signal transmitter, and the blocking inputs and the answer, respectively, with the first and second outputs of the interrupt processing unit, the third, fourth outputs of which are connected respectively to the information inputs of the third and fourth control signal transmitters, and the sample inputs and the interrupt request block of the pre-processing unit are connected to the outputs first l

the second control signal receivers, the inputs of which are the corresponding inputs of the device for connecting to the microcomputer trunk and the peripheral device highway, the outputs of the first, second and third transmitters are the corresponding outputs of the device for connecting to the microcomputer trunk, the inverse output of the control trigger is connected to the enable inputs of the third and the fourth control signal transmitters, the output of the latter is the output of the device for connecting peripheral devices to the highway c, the enable inputs of the first and second control signal transmitters are connected to the first group of outputs of the control signal amplifier unit, the first input of the direction selection of the first and the input of the direction selection of the third control signal switch, the enable inputs of the second and third control signal switches are connected to the direct the output of the control trigger, the sync input of which is connected to the sync input of the interrupt processing unit and the third output of the control signal conversion unit, the zero-bit input whose addresses and the address input of the interrupt processing unit are connected to the first group of information inputs and outputs of the information and address signal switch, the data reading input of the interrupt processing unit is connected to the first group of information inputs and outputs of the first control signal switch and the first input of the AND gate, the second the input connected to the fourth output of the control signal conversion unit, the data reading input of which is connected to the first input of the OR element and to the second group of information inputs the outputs of the first control signal switch, the second direction selection input of which is connected to the second group of outputs of the control signal amplifier unit, the direction selection input of the second control signal switch, the third input of the AND gate and the second input of the OR element, the installation input of the control trigger is connected with the second group of outputs of the node of the amplifiers of the control signals, the input address of the vector of the interrupt processing unit is the input of setting the address of the interrupt vector of the device, while the conversion unit The control signal bar contains three OR elements, three AND-NOT elements, four AND elements, five

delay elements, two elements NOT. DVZ trigger and two OR-NOT elements, the first and second groups of information inputs of the block, the first and second groups of outputs of block 5, the blocking input of the block, the inputs of the zero bit of the address, response and reading of the block, from the first to the fourth outputs of the block, and the outputs of the first Elements OR and AND NOT, the first input. Of the first element

0 OR are connected respectively to the input of the first delay element and the first input of the first element. The output of the first element is NOT connected to the first input of the second AND-NOT element, the output connected through 5 the second delay element to the first input of the third AND-NOT element, the second input of which is connected to the inverse the output of the first trigger, the sync input connected to the output of the third delay element, pr 0 mine and the inverse outputs of the second trigger are connected to the first inputs of the second and third elements And, respectively, the outputs of which dklyucheny to first inputs of first and second OR-NO

5 respectively, the second inputs of which are connected to the output of the second element NOT, the output of the fourth delay element is connected to the first input of the second OR element, the output of which is the first output of the block, the output of the fifth delay element is connected to the first input of the fourth AND element, the second input of which is the block lock input, the first input and output of the third

5 OR elements are respectively the response input and the fourth output of the block, the read input of the block is connected to the second input of the second OR element and is the second output of the block, the outputs of the first

0. The AND element, the first delay element, the fourth And element, and the corresponding bit of the second group of information inputs of the block form the second group of outputs of the block, the first and second inputs of the first 5 AND gate NOT connected to the first and second inputs of the first OR element, respectively the input of the first element And and the input of the fifth delay element connected to the third output of the block form the second group of information inputs of the block, the reset input of the first trigger connected to the clock input of the second trigger, the inputs of the first ele NOT cient and the third element

5 delays, the second input of the second AND-NOT element connected to the information input of the first trigger, with the second inputs of the second and third AND elements, the output of the second NOT connected to the input of the fourth delay element and the second input of the third OR element form the first group of information inputs of the block , the outputs of the first element OR-NOT and the second element OR-IE, the outputs of the third elements NAND and OR and the input of the first element NOT connected to the first group of information inputs of the block form the first group of outputs of the block, and the block The interrupt operation contains an address setting input for reading a vector, an address decoder, a trigger, the first and second AND elements, with the first through third delay lines, the NOT element, address input, sample input, block clock input, block read and interrupt request inputs, from first to the fourth outputs of the block, the trigger synchronization input being connected via the first delay element to the block smnh input and the trigger reset input, the information input and the direct output of the address decoder and the first input of the first element connected respectively the And, whose output through the second and third delay elements is connected to the fourth and second outputs of the block, the first input of the second AND element is connected through the NOT element to the output of the first And element, and the output is the third output of the block, the second inputs of the first and second And elements and the inverse trigger output are respectively the read and interrupt request inputs and the first block output.

Comparable analysis by the prototype shows that the claimed device is characterized by the presence of new elements, namely, two control signal switches, an OR element, an NAND element, an AND element, an NAND element, a control signal conversion unit, an interrupt processing unit, four trunk control signal transmitters, two control signal receivers and their communications with other elements. Thus, the claimed device meets the criteria of the invention of novelty,

Comparison of the claimed solution with other technical solutions shows that all of these elements are widely known. However, when they are introduced, in connection with other circuit elements, into a device for interfacing a microcomputer trunk with a peripheral trunk, they lead to the expansion of the functionality of the proposed interface device.

Expansion of operational capabilities is obtained due to the fact that peripheral devices connected to

MPI bus according to GOST26765.51-86 can be connected to the system line of micro-computer Electronics MS0585.

Fig. 1 is a functional diagram of a device for interfacing a microcomputer trunk with a peripheral trunk; Fig. 2 is a functional diagram of a control signal conversion unit; Fig. 3 is a functional diagram of an interrupt processing unit.

A device for interfacing a microcomputer trunk with a peripheral trunk contains (Fig. 1) a switch 1 for information and address signals, a first switch 2 for control signals, a node 3 for control signal amplifiers, a trigger 4 for control, an element NOT

5, second 6 and third 7 control signal switches, control signal conversion unit 8, interrupt processing unit 9, AND element 10, AND-NOT element 11, OR element 12, first 13 and second 14 control signal receivers, first 15 second 16, third 17 and fourth 18 control signal transmitters, microcomputer highway 19, peripheral devices highway

20, the start input of the device 21, the input of the address of the interrupt vector 22. The first and second groups of information inputs and outputs of the switch 1 information and address signals

are the corresponding input-output groups of the device for connecting to the microcomputer line 19 and 20 peripheral devices, the first and second control signal information-output groups of the control signal switch 2 are the corresponding input-output groups of the device for connecting to the microcomputer mains 19 and 20 peripherals and

are connected to lines x 10 and 20 to the lines Reading data (in the terminology of microcomputer interfaces and peripheral devices - an RF signal), and Device Selection (VU), the first groups of information inputs and outputs of the control signal amplifier unit 3 are the corresponding input groups and outputs of the device for connecting to the line 19 of the microcomputer and are intended for transmitting to the device the signals Capture Resolution (REM), Installation (UST) and for transmitting to the line 19 signals Request of the trunk (GP), Request Confirmation (PP), Avari of the power supply (AIP), the second group of information inputs and outputs of the control signal amplifier unit 3 are the corresponding groups of inputs and outputs of the device for connecting peripheral devices to the highway 20 and are designed to transmit ZM, PZ, AIP signals to the device and to transmit to highway 20 signals REM and TSI, the information input of the trigger 4 is the input of the start of the device, the direct output of the trigger 4 is connected to the resolution inputs of the first switch 2 of the control signals, node 3 of the control amplifiers signals and switch 1 information and address signals, the first input of the direction selection of the first switch 1 information and address signals is connected to the output of the element NOT 5, the outputs of the elements AND 11 and OR 12 are connected respectively to the first and second inputs of the element And 10, the output connected to the second input of the selection of the direction of the switch 1 information-address signals and the input of the element NOT 5, the group of information inputs / outputs of the second 6 and third 7 control signal switches are the corresponding groups of inputs moves to exclude 19 microcomputer lines and 20 peripheral devices and are connected on the 19 microcomputer lines to Exchange Synchronization (OBM) lines, Answer (OTV), Low Byte Record (DZP-MB), High Byte Record ( DZP-SB), Address output cycle or output (VAD), and on the highway 20 peripheral devices - to the OBM, OTV, Data Record (DZP) lines, Record flag (PZP), and the groups of information inputs and groups of outputs, respectively, with the first and second groups of outputs, the second and first groups of information inputs of the control transformation block signals, the first and second outputs of which are connected respectively to the information inputs of the first 15 and second 16 transmitters of control signals, and the blocking and response inputs, respectively, to the first and second outputs of the interrupt processing unit 9, the third and fourth outputs of which are connected respectively to the information inputs third 17 and fourth 18 transmitters of control signals, and the inputs of the sample and interrupt request of the interrupt processing unit 18 are connected to the outputs of the first 13 and second 14 control receivers latter is present, the inputs of which are respective inputs for connecting the apparatus to the pipeline 19

microcomputers and magistrabs 20 peripheral devices, the outputs of the first 15, second 16 and third 17 transmitters are the corresponding outputs of the device for 5 connecting to the microcomputer line 19, the inverse output of the control trigger 4 is connected to the enable inputs of the third 17 and fourth 18 transmitters of control signals, the last

0 is the output of the device for connecting peripheral devices to the highway, the enabling inputs of the first 15 and second 16 control signal transmitters are connected to the first group 5 of the control signal amplifier unit 3 and the control inputs of the first 2 and third 7 control signal switches, which enable inputs second 6 and third 7 switches

0 control signals are connected to the direct output of the control trigger 4, the sync input of which is connected to the sync input of the interrupt processing unit 9 and the third output of the conversion unit

5 control signals 8, the address zero-bit input and the address input of the interrupt processing unit are connected to the first group of information inputs / outputs of the switch 1 information and address signals, the data reading input of the interrupt processing unit 9 is connected to the first group of information inputs and outputs 4 of the first switch 2 control signals and the first input

5 of the AND-NOT element 11, the second input connected to the fourth output of the control signal conversion unit 8, the data reading input of which is connected to the first input of the OR element 12 and

0. the second group of information inputs and outputs of the first control signal switch 2, the direction selection input of which is connected to the second group of outputs of the amplifier amplifier unit 5 of the control signals 3, the third input of the I-IE 11 element and the second input of the OR element 12, the installation input of the control trigger 4 is connected to the second group of outputs of the control signal amplifier unit 3, the input address of the vector of the interrupt processing unit 9 is the input of setting the address of the interrupt vector of the device.

Control conversion unit

5 signals contains (figure 2) three elements OR 23, 24, 25, three elements NAND 26 ... 28, four elements AND 29, 30, 31, 32, five delay elements 33.,. 35, 36 , 37, two elements NOT 38, 39, two triggers 40, 41 and two cements IL AND NOT 42 and 43, the first and second

groups of information inputs of block 44, 45, first and second groups of outputs of block 46, 47, block input of block 48, zero-bit inputs of address 49, response 50, and reading of block 51, the first to fourth outputs of block 52 ... 55, and the outputs of the first elements OR 23 and AND NOT 26, the first input of the first element OR connected respectively to the input of the first delay element 33 and the first input of the first element AND 29 the output of the first element NOT 38 is connected to the first input of the second element AND NOT 27, the output connected through second delay element 34 to the first input of the third e element AND-NOT 28, the second input of which is connected to the inverse output of the first trigger 40, the sync input connected to the output of the third delay element 35, the direct and inverse outputs of the second trigger 41 are connected to the first inputs of the second 30 and third 31 And, respectively, the outputs of which are connected to the first inputs of the first 42 and second 43 elements 1LLI-NOT, respectively, the second inputs of which are connected to the output of the second element NOT 39, the output of the fourth delay element 36 is connected to the first input of the second element OR 24, the output of which is is the first block output 52, the output of the fifth delay element 37 is connected to the first input of the fourth AND element 32, the second input of which is the block input 48 of the block, the first input and output of the third OR element 25 are the response input and fourth block output 55, the read input 51 of the block is connected to the second input of the second OR element 24 and is the second output 35 of the block, the outputs of the first AND element 29, the first delay element 33. of the fourth AND element 32 and the corresponding bit of the second group of information inputs of the block form a second group of outputs 47. of the block, the first and second inputs of the first AND-NOT element 26, connected respectively to the first and second inputs of the first OR element 23, the second input of the first AND element 29 and the input of the fifth delay element 37, connected to the third output 54 of the block form a second group of information inputs of the block, the reset input of the first trigger 40 connected to the sync input of the second trigger 41, the inputs of the first element HF and the third delay element., the second input of the second element AND-NOT 27 connected to the information input of the first trigger 40 with the second inputs of the second 30 and third 31 elements And, the input of the second

element 39, connected to the input of the fourth delay element 36 and the second input of the third element OR 25 form the first group of information inputs 44 of the block,

the outputs of the first element AND AND AND NOT 42 and the second element OR AND NOT 43 are connected, the outputs of the third elements AND NOT 28 and OR 25 and the input of the first element NOT 35 connected to the first group of information inputs

44 blocks, form the first group of outputs 47 of the block.

The interrupt processing unit 9 contains (FIG. 3) an address decoder 56, a trigger 57, first and second elements AND 58, 59, s

the first along the third delay line 60. ,, 62, element NOT 63, address input 64, sample input 65, clock input of block 66, read inputs of block 67 and interrupt request 68, first to fourth outputs of the block

69 ... 71, and the trigger input of the trigger 57 is connected through the first delay element 60 to the sync input of the block and the reset input of the trigger 57, the information input and the direct output connected respectively to the output of the address decoder 56 and the first input of the first element And 58, the output of which is through the second 61 and the third 62 delay elements are connected to the fourth 72 and second 70 outputs of the block, the first input of the second AND element 59 is connected through the element 63 to the output of the first AND element 58, and the output is the third output of the block 72, the second inputs of the first 58 and second 59 ale The AND and trigger inverse outputs are respectively the read and interrupt request inputs and the first block output.

The switch 1 information-address signals and the first switch 2 control signals when applying to the input of the permission of a high level of voltage are disconnected from both lines, and when

applying a low voltage enable input, the direction of transmission is determined by the voltage levels at the direction selection inputs. When applying to the first input low direction selection

voltage, and to the second input of the direction selection - high level, the switches transmit information from the first group of I / O to the second (that is, from the line 19 of the microcomputer to the line 20 of peripheral devices), when a high level of direction is applied to the first input of the choice of direction to the first input of direction selection - low level, the switches transmit information from the second (input-output groups

on the first (that is, from the line of 20 peripheral devices to the line of 19 micro-computers). Switches 1 and 2 can be implemented on K559YPZ chips.

The second 6 and third 7 control signal switches are disconnected from both highways when applying a high-voltage enable input, and when applying a low-voltage enable input, the direction of transmission is determined by the voltage levels at the direction selection inputs. When a high voltage direction selection input is applied to the input, the switches transmit information from the information input-output group of information to the output groups (from the corresponding highway to the control signal conversion unit 8), and when the low voltage direction selection input is input, the switches transmit information from a group of inputs to a group of information inputs / outputs (from a block 8 for converting control signals to a corresponding highway). Switches 6 and 7 can be implemented on K559ILZ microcircuits. Trunk transmitters 15 ... 18 perform a logical AND-NOT function on the signals at their inputs and are K559IP1 microcircuits.

The control signal amplifiers block 3 transmits information from the first group of information inputs to the second group of information outputs and from the second group of information inputs to the first group of information outputs when low voltage level resolution is applied to the input. When the voltage level is enabled, the first and second groups of information outputs are disconnected from the mains. Block 3 can be implemented on chips K559IP1 and K559IP2.

The delay elements that make up the device can be implemented as integrating RC circuits.

Address decoder 56 can be implemented using two comparison schemes implemented in the form of K155SP1 microcircuits,

The device operates as follows.

At the beginning of the operation, the TSI signal coming from the second group of outputs of block 3, trigger 4 is set to a single state. If there is a high level of voltage at the input 21 of the start, trigger 4 will remain in a single state upon arrival at the sync input

OBM signals, therefore, at the direct output of trigger 4 is a high-level signal, and at the inverse output is a low-level signal. As a result, the switch 1 information-address signals, the first 2, second 6 and third 7 will be disconnected control signal switches (since a single

10 disconnecting level), fleas of control signal amplifiers 3, as well as third 17 and fourth 18 transmitters of control signals (a zero disconnecting level arrives at their resolving inputs).

5 The PZ signal coming from the first group of outputs, in this case, will be low and therefore the first 15 and second 16 transmitters of control signals will be disabled. Thus in the case

0 the presence at the input of the start-up device of the high level device 21, on the other hand, the device will be disconnected from the lines 19 and 20 and will not affect their operation.

In operating mode, input 2 i start

5, a low level signal is generated. Upon the arrival of the first OBM signal, trigger 4 is set to zero. As a result, the inverse output is a high level signal. Therefore, through the control unit 3, the signals REM, TSI will be transmitted from the line 19 of the microcomputer to the highway 20 of peripheral devices, and the signals ZM, PZ, AIP will be transmitted

5 in the opposite direction.

The direction of transmission of the information-address signals depends on the signal level at the output of the And 10. element. at the voltage level at the §1 input of this element, information and address signals will be transmitted from the line 19 of the microcomputer to the line 20 of peripheral devices, and at a low level in the opposite

5 direction

The transmission of information and address and other control signals depends on the operating mode of the device. The device can work in the following

0 modes:

1) software, i.e. appeal of micro-computers to devices on the highway of peripheral devices;

2) interruption mode of the mic-5 rocomputer program of the device connected to the highway 20;

3) the mode of direct access to the memory of the microcomputer by a device connected to the highway 20 of peripheral devices.

Consider the signal transmission by the interface device in each of these modes.

In the program mode of operation and the interrupt mode, the PZ signal is in a passive state, therefore, the low input to the direction selection of the first switch of the control signals 2, to the input to select the direction of the second switch of the control signals 7 and to the enable inputs of the first 15 and second 16 transmitters voltage level from the first group of outputs of the amplifier block and control signals 3, and to the second input of the direction selection of the first switch of control signals 2, to the input of the direction selection of the first switch The input signal 6 receives a high voltage level from the second group of outputs of the control signal amplifier unit 3. In this case, the first 2 control signal switch transmits the signals of the blackbody and the control unit from the main line 19 of the microcomputer to the line 20 of peripheral devices, the second 6 switch control signal transmits OBM, DZP, MB, DZP SB, VAD signals from the line 19 of the microcomputer to the control signal conversion unit 8, and the OTV signal in the opposite direction, the third control signal switch 7 transmits OBM, DZP, PZP signals from the 8 conversion unit audio control signals on line 20, peripherals, and signal CTE in the reverse direction. In these two operating modes, the signals Address output cycle or output (ACV), Data (D) from the outputs of the first 15 and second 16 transmitters of control signals are not received to the main line 19 of the microcomputer.

In the program mode and the interrupt mode, the control signal conversion unit 8 transmits the OBM signal from the second control signal switch 6 to the third control signal switch 7, and the OTV signal from the opposite direction. and also converts the signals of the DZP MB, DZP SB, VAD, coming from the second switch 6 of the control signals, into the signals of the DZP, PZP and transmits them to the third switch 7 of the control signals.

The direction of transmission of information and address signals depends on the voltage level at the output of the And 10 element. In the above two modes, the second input of the And 10 element will have a high voltage level from the output of the OR element 12, since the second input of the latter receives a high level voltage from the second group of outputs of the block of control signal amplifiers 3. When

the signal level at the output of the AND 16 element will repeat the signal level at the output of the AND-NOT 11 element, which, in turn, will depend on the signal levels

DCT on the first line 19 of the microcomputer and the OTV signal coming from the interface device to the line 19 of the microcomputer, i.e. unit 1 in program mode and interrupt mode will transmit the addressable signals from the peripheral device highway 20 to the microcomputer highway 19 in a cycle of reading from the microcomputer side of the device registers on the highway 20 or reading the device vector address. AT

In the remaining 5 cases (address or recording cycles), information and address signals will be transmitted from the microcomputer line 19 to the peripheral device line 20,

0 In interrupt mode, the device operates as follows.

The Interrupt Request signal (CRL) on the peripheral device trunk 20 is transmitted to the microcomputer trunk 6 on the Exchange Request line (30). As a result, the microcomputer goes to interrupt processing. The interrupt processing unit 9 converts the read cycle of the register of the interface device on the microcomputer highway 19 into

0 interrupt vector read cycle on line 20 of peripheral devices. At the same time, the OBM signal is passed to the peripheral devices highway 20, the DST signal is passed to the peripheral devices highway 20, and after a certain time, the block 9 generates an Interrupt Resolution (RRP) signal entering the peripheral devices highway 20, the device that issued the request and

0 receiving the signals BHT and PRR, sets its interrupt and the OTV signal, which is transmitted to the highway 19 of the microcomputer. Thus, when accessing the vector address of the device, the microcomputer reads

5 interrupt vector.

When reading the vector of the device, the interface device provides for the generation of an OTV signal in the absence of an OTV signal from a peripheral line 20

0 devices (in this case, the microcomputer reads the status of the information and address lines of the trunk of 20 peripheral devices). This mode can be used to debug devices on the line of 20 peripheral devices.

In direct access mode, the initiating device in this mode sets the EM signal, which is transmitted to the microcomputer highway 19. The microcomputer generates an REM response signal, and the device sets the PZ signal and picks up the EM signal, as a result of which the microcomputer picks up the REM signal and transfers control of line 19 to the device. The device starts the exchange operation on the trunk.

Consider the operation of the device in this mode. The PZ signal is in the active state, therefore, a high voltage level from the first group of outputs is supplied to the first input of the direction selection of the first control signal switch 2, to the direction selection input of the second control signal switch 7 and to the enable inputs of the first 15 and second 16 transmitters a block of control signal amplifiers, 3 and a level is received at the second direction input of the first control signal switch 2, at the input of the direction selection of the first control signal switch 6 of the transmitter April voltage to the second group of amplifiers output unit 3. In this case, first switch 2 transmits the control signals and TDM signals DCHT line 20 with the peripheral devices on line 19 of the microcomputer. The third control signal switch 7 transmits OBM, DZP, PZP signals from the line 20 of peripheral devices to the control signal conversion unit 8, and the OTV signal is in the opposite direction. The second control signal switch 6 transmits OBM, DZP MB, DZP SB, VAD signals from the control signal conversion unit 8 to the microcomputer highway 19. and the OTV signal is in the opposite direction. The first 15 and second 16 transmitters transmit signals D and ACV generated by block 8 to the line 19 of the microcomputer.

The direction of transmission of information and address signals depends on the voltage level at the output of the And 10 element. In the considered mode, since the PZ signal is active, a high level signal from the second group of outputs of the control amplifier amplifiers node is received at the second input of I / I 10 3 and the signal level at the output of AND element 10 will repeat the signal level of the DCT from the side of the line 20 of peripheral devices. Thus, in reading cycles, the first switch 1 transmits information and address signals from the microcomputer highway 19 to the peripheral device highway 20, and in other cases (address cycles, recording cycles), the information and address signals will be transmitted from the peripheral device highway 20 to the highway 19 microcomputers.

The control signal conversion unit 8 operates as follows.

In the program mode of operation and the interrupt mode, all signals from the second group of information inputs of block 45 are used, except for the OTV signal arriving 5 via line 45.4, and the OTV signal from input 45.4 is also used. The remaining signals, although processed by the unit, are not transmitted by the control signal switches 6 and 7 on the trunk. Consider the conversion of the signals used.

The OBM signal arrives from the second group of information inputs of block 45 via line 45.1 to the fifth delay element 37, is delayed by it, and passes to the first input

5 of the fourth element And 32, the second input of which receives a signal from the blocking input of block 48. This signal is generated in block 9 of the interrupt processing and has a high level all the time, except

0 address to the interrupt vector address of the device for organizing the procedure for reading the interrupt vector. The delay time of the fifth delay element 37 is selected to be longer than the response time of the vector address selection circuit 5. Thus, the OBM signal is transmitted from the second group of information inputs of block 45 to the second group of information outputs of block 47 along line 47.4 in all cases, except

0 read interrupt vector from a line of 20 peripheral devices.

In addition, the control signal converting unit generates the DZP and PZP signals. The signal of the remote sensing signal is generated at

5 output of the first delay element 33 and is set to the active state (high level) after a time determined by the delay time of the delay element 33 after the occurrence at the inputs of the first element OR 23 of one of the signals of the DZP MB on line 45.1 or the DZP SB on line 45 ., Delay element 33 is designed so that the PPP signal in the case of recording a word is absent before the signal

5 DZP and that the device mistakenly did not accept the operation of writing a word for the operation of writing a byte.

The PPP signal is generated when there is a high (active) level of the VAD signal on line 45.3 and a passive (low) level of at least one of the signals of the DZP MB or DZP SB at the inputs of the first AND-NOT 26 element.

An OTV signal is output

5 of the third AND-NOT 25 element, if line 44.4 receives a high-level response signal from the line 20 of peripheral devices or a response signal from block 9 coming from the input of the response 50 to the first input of the third element OR 25.

In the direct memory access mode, all signals from the first group of information inputs 44 are used, except for the OTV signal coming on line 44.4, and the OTMS signal coming in on line 45 4 is used. The remaining signals, although processed by the unit, are not transmitted by the switches b and 7 control signals on lines 19 and 20. Therefore, we consider the transmission of the signals used.

The OTV signal comes from the second group of information inputs of block 45 on line 45 4 to the second group of outputs of block 47 on line 47.3, and the signal OBM is transmitted from the first group of information inputs of block 45 on line 45.4 to the second group of outputs of block 47 on line 47.3, and the signal MBP is transmitted from the first group of information inputs 44 on line 44.1 to the first group of outputs 46 on line 46.5.

The VAD signal is generated as a result of processing the OBM and PZP signals coming from the first group of information inputs of block 44 along lines 44.1 and 44.2, respectively. At low levels of these signals, a high level signal is present at the output of the third I-NOT 28 element, because there is a high level at both its inputs (trigger 40 is in the zero state, and at the outputs of the second AND-NO 27 element and the second delay element 34 is a high level).

Consider the generation of a VAD signal during a write operation.

When a high signal level appears on line 44.2, the output of the AND-NOT 27 element displays a low signal level, which passes through the delay element 34 (the voltage drop from high to low passes through the element 34 with almost no delay) to the first exit NAND 28. Line 46.1 shows a high voltage level. Thus, in the address cycle of the write operation, the VAD signal on line 46.1 is at a high level.

When a high level of the OBM signal appears on line 44.1, the low level is removed at the installation input of the trigger 72, and after a while, determined by the delay element 70, the voltage drop appears and at a high level on the line 44.2, the trigger 41 is set to a single state for the duration of the OBM signal, and thus a high level is maintained at the output of the AND-NO 28 element, regardless of the level of the PPP signal on line 44.2.

At the same time, the OBM signal is inverted by the HE 38 element and causes a high level at the output of the AND-HE 27 element, which is delayed by the delay element 34 (its delay time exceeds the delay time of the element 35 and the setting

flip-flop 40) and does not affect the state of the PPP signal on line 46.1.

In the address cycle of the read operation on line 44.2, there is a low voltage level, trigger 40 is not set to a single state under the action of the signal on line 44.1 and the VAD signal on line 46.1 is low (passive state) regardless of the change in signal level PPP on line 44.2 during

5 of the operation of the OBM signal on line 44.1 (for the line 20 of peripheral devices, the signal level of the RPC signal in the data cycle of the read operation can have any value).

0 Signals of the DZP MB and DZP SB are generated on lines 46.2 and 46.3 as follows.

In the address cycle of each exchange operation, the trigger 41 is set to a single or zero state depending on or the voltage level on the zero bit line 49 of the address. If in the data transfer cycle the signal on line 44.2 of the PPP is at a low level (i.e., an information word is being recorded), then the outputs of the elements 30 and 31 will have a low signal level, regardless of the state of trigger 41.

If there is a high level PPP signal in the data transfer cycle on line 44.2

5, the voltage at one of the AND 30 or 31 elements (depending on the state of the trigger 41) will have a high voltage, and at the other a low voltage level. The output signals of the elements And 30 and 31

0 are gated by the DZP signal arriving on line 44.3 and inverted by the OR-NOT 42 and 43 elements, the output signals of which are received on lines 46.2 and 46.3, respectively.

5

Block 8 converting control signals in direct access to memory mode produces signals D and ACV, which are supplied to the first 52 and second 53 outputs

0 of block 17. The ADC signal repeats the signal of the DCT received from read input 51 of the block. The active (high) level of signal D is generated when the active (high) level of one of the signals of the DCT or DZP, and

5, the output signal repeats the DTT signal and is delayed for a certain time (determined by the microcomputer interface) relative to the DZP signal

Block 9 interrupt processing operates as follows

The device on the peripheral device line 20 sets an STL signal to the interrupt request input 69 of the block. Since there is no reference to the device vector address in program mode, trigger 57 is in the zero state and a low pressure signal is present at its direct output. As a result, a low-level signal is present at the output of element 1/1 58, and a high signal level is received at the first input of AND element 59. Therefore, the ZPR signal from input 68 through element I 59 enters the third output 71 of the block and into the main line 19 of the microcomputer as signal 30. The microcomputer, having received signal 30, in the interrupt processing program performs the operation of reading the address of the device vector, the address of which is set at the input 22 (applying certain signal levels to the inputs of the address selector 56).

In the case of applying to the input of the address selector 56 an active sample signal on line 65 (determining that the address on the microcomputer highway 19 is included in the specified address zone), and coincidence with the first to seventh bits of the address coming on line 64 with those specified on the input 22, a high voltage level is generated at the output of the address selector 56. Upon receipt of the OBM signal at sync input 66, the zero signal of the trigger 57 is taken, and after a while an active voltage drop is received through its delay element 60 through its delay element 60 tim from low to high. If there is a high voltage level at the information input of the trigger 57 coming from the output of the address selector 56, the trigger 57 is set to a single state for the duration of the OBM signal. The signal from the inverted output of flip-flop 57 is fed to the first output 69 of the block and prevents the OBM signal from passing to the highway 20 of peripheral devices. A high level signal from the direct output of the trigger 57 is supplied to the first input of the first element And 58.

After the DTT signal is received on the line 19 of the microcomputer of the microcomputer, it is transmitted through the switch 2 to the majstral 20 of the peripheral devices and arrives from the second group of inputs / outputs of the unit 2 at a high input level to the read input 67 of the unit. As a result, the output of the And 58 element displays a high signal level. which enters through the element NOT 63 to the first input of the AND element 92 and blocks the passage to the third output 71 of the interrupt request signal block. The signal from the output of the element And 58 also goes to the input of the second delay element

61 and after some time (determined by the requirement of the line 20 of peripheral devices), it enters the fourth output of block 72 and on the PRR line of the line 20 of 5 peripheral devices.

The third delay element 62 delays the low to high drop. The delay time of element 62 is chosen sufficiently large (about 5 μs), so that when

0, the OTV signal is received from the line of 20 peripheral devices of the microcomputer and will remove the RF signal and the differential from the low voltage level will not pass to the second output of block 70 (delay element 62 passes the voltage difference from high to low with almost no delay). the OTV signal from the line 20 of peripheral devices (for example, in the case of testing the line 20) produces a high signal level at the second output of block 70 and information-address signals from the line 20 of peripheral devices through a switch 1 are transmitted to the relevant line trunk 19

Claims (3)

5 microcomputers, while in the line 19 of the microcomputer also receives the OTV signal. SUMMARY OF THE INVENTION 1. A device for interfacing a microcomputer trunk with a peripheral trunk, comprising a switch for information and address signals and a first switch for control signals, the first and second groups of information inputs and outputs of which are respectively 5 existing groups of inputs and outputs of the device for connecting microcomputers and peripheral devices to the backbones, a node of control signal amplifiers, the first groups of information inputs and outputs 0 of which are the corresponding groups of inputs and outputs of the device for connecting to the microcomputer trunk, and the second groups of information inputs and outputs are the corresponding 5 groups of inputs and outputs of the device for connecting peripheral devices to the highway, a control trigger, the information input of which is the start input of the device, and an element NOT, moreover 0 the direct trigger output is connected to the resolution inputs of the first control signal switch, the node of control signal amplifiers and the information address switch, the first 5, the direction selection input of which is connected to the output of the element NOT, it is necessary that, in order to expand the functionality of the device by ensuring that peripheral devices are connected to the trunk device, which is identical in type to the mainframe of the microcomputer, it introduced the second and third control signal switches, a control signal conversion unit, an interrupt processing unit, an AND element, an NAND element, an OR element, two control signal receivers, four control transmitters signals, and the outputs of the AND-NOT and OR elements are connected respectively to the first and second inputs of the AND element, the output of the informational-addressing signals connected to the second input of the choice of the direction of the switch to the input of the element NOT, the group of information in the outputs of the second and third control signal switches are respectively the INPUT groups of the device for connecting microcomputers and peripheral devices to the main lines, and the groups of information inputs and output groups are connected respectively to the first and second groups of outputs, the second and first groups of information inputs of the block conversion of control signals, the first and second outputs of which are connected respectively to the information inputs of the first and second transmitters of control signals, and the inputs blocking and response - respectively, with the first and second outputs of the interrupt processing unit, the third and fourth outputs of the interrupt processing unit are connected respectively to the information inputs of the third and fourth transmitters of control signals, the inputs of the sample and interrupt request of the interrupt processing unit are connected to the outputs of the first and second receivers control signals, the inputs of which are the corresponding inputs of the device for connecting to the mains of the microcomputer and the highway of peripheral devices, the outputs are not The first, second and third transmitters are the corresponding outputs of the device for connecting to the mainframe of the microcomputer, the inverse output of the control trigger is connected to the enable inputs of the third and fourth control signal transmitters, the output of which is the output of the device for connecting peripheral devices to the highway, allowing the inputs of the first and the second control signal transmitters are connected to the first group of outputs of the control signal amplifier unit, the first input of the direction selection of the first and input, selecting the direction of the third control signal switch, the enable inputs of the second and third control signal switches are connected to the direct output control trigger, the sync input of which is connected to the sync input of the interrupt processing unit and the third output of the control signal conversion unit, input the zero bit of the address of which and the address input of the interrupt processing unit are connected to the first group of information inputs and outputs of the switch information and address signals, the data read input 0 of the interrupt processing unit is connected to the first group of information inputs and outputs of the first control signal switch and the first input of the NAND element, the second input connected to the fourth and fifth output of the control signal conversion unit, the data reading input of which is connected to the first input of the OR element and the second group of information inputs and outputs of the first switch 0 control signals, the second input of the direction selection of which is connected to the second group of outputs of the node amplifier control signals, the input of the choice of direction of the second control switch 5 signals, the third input of the AND element and the second input of the OR element, the installation input of the control trigger is connected to the second group of outputs of the node of the control signal amplifiers, the vector address input 0, the interrupt processing unit is the input of setting the address of the device interrupt vector. 2. The device according to claim 1, with the proviso that the control signal conversion unit 5 contains three OR elements, three AND-NOT elements. four AND elements, five delay elements, two NOT elements, two triggers and two OR-NOT elements, the first and second groups of information 0 block inputs, the first and second groups of block outputs, block block input, zero-bit inputs of the address, response and reading of the block, the first to fourth block outputs, the outputs of the first elements OR 5 and 1/1-NOT, the first input of the first OR element is connected respectively to the input of the first delay element and the first input of the first AND element, the output of the first element is NOT connected to the first input of the second NAND element, the output connected through the second delay element to the first the input of the third AND-NOT element, the second input of which is connected to the inverse output of the first trigger, the sync input connected to 5 to the output of the third delay element, the direct and inverse outputs of the second trigger are connected to the first inputs of the second and third elements AND, respectively, the outputs of which are connected to the first inputs of the first and second elements OR AND NOT, respectively, the second inputs of which are connected to the output of the second element NOT, the output of the fourth delay element is connected to the first input of the second And / 11/1 element, the output of which is the first output of the unit, the output of the fifth delay element is connected to the first input of the fourth And element, the second input of which o is the block lock input, the first input and output of the third OR element are respectively the response input and the fourth output of the block, the read input of the block is connected to the second input of the second OR element and is the second output of the block, the outputs of the first element I. of the first delay element, the fourth element And and the corresponding bit of the second group of information inputs of the block form the second group of outputs of the block, the first and second inputs of the first element AND NOT connected respectively to the first and second inputs of the first element And LI, the second input of the first element And and the input of the fifth delay element connected to the third output of the block, form the second group of information inputs of the block, the reset input of the first trigger connected to the sync input of the second trigger, the inputs of the first element NOT and the third delay element, the second input of the second AND element NOT connected to the information input of the first trigger, with the second inputs of the second and third AND elements, the input of the second element NOT connected to the input of the fourth delay element, and the second input of the third OR element forms the first group of information inputs of the block, the outputs of the first and second elements OR-NOT, the third elements AND-NO and OR and the input of the first element NOT connected to the first group of information inputs of the block form the first group of outputs of the block. 3. The device according to claim 1, wherein the interrupt processing unit comprises an address setting input for reading a vector, an address decoder, a trigger, first and second AND elements, from the first to the third delay line, element NOT, address input, sample input, block sync input, block read and interrupt request inputs, from the first to fourth block outputs, the trigger sync input being connected via the first delay element to the sync input block and trigger reset input, information input and direct output connected respectively to the output of the address decoder and the first input of the first AND element, the output of which is the second and third delay elements are connected to the fourth and second outputs of the block, the first input of the second element And is connected through the element NOT to the output of the first element And, and the output is the third output of the block, the second inputs of the first and second elements And and the inverse trigger output are respectively read and interrupt request inputs and the first block output. Fig / fr53 45.4 29th B7.3 47 FIG. 2 85 N. 22 56 67 Fig.Z 69 years 70 71