SU1236493A1 - Interface for linking processor with multiblock memory - Google Patents

Abstract

The invention relates to computing technology and can be used to increase the amount of RAM in the construction of computer systems based on mini-computers and micro-computers. The aim of the invention is to expand the field of application of the device by providing the processor with a memory whose address space significantly exceeds the capabilities provided by the address word format of the processor. The device contains a segment decoder, an address decoder, an array number register, channels of channel transmitters and receivers, a data bus switch and lower-order address bus bits. 2 Il. with Q 1C 00 O) iJ W Co

Description

The invention relates to computing and can be used to increase the amount of RAM in the construction of computer systems based on mini and micro computers.

The aim of the invention is to expand the field of application of the device by providing the processor with a memory whose address space significantly exceeds the capabilities provided by the processor address word format, as well as the survivability of the system including the proposed device and. multi-block memory.

FIG. 1 shows a block diagram of the device, FIG. 2 illustrates an example of a system structure including a device and a multi-block memory.

Device 1 (Fig. 1) contains a segment decoder 2, address decoder 3, register 4 array numbers, node 5 channel transmitters, nodes 6 and 7 channel receivers, switch 8 data buses and low-order address bits, buses 9 and 10 the output of the low and high bits of the memory address of the device, the bus 11 and 12 of the second and first information inputs-outputs of the device, lines 13-15 of the output group of the memory access signals of the device, the bus 16 lower address bits, the group of control inputs 17 of the device , tires 18 high-order address addresses, output 19 of the decoder 2, the second output 20 of the switch 8, the outputs 21 and 22 of the decoder 3, the signal line 23 Record (RFP), the signal line 24 Read (THU) and the signal line 25 Synchronize the address (AHA) group of control inputs 17, processor channel 26 and the block 27 memories.

The device is intended for organizing multi-block memory (FIG. 2 and contains interface 1, memory blocks 27, memory banks 28, with all inputs-outputs 29 of the interface device being paralleled and connected to processor channel 26, and the outputs 30 of the device 1 are connected to the inputs-outputs of the memory blocks 27.

The device works as follows.

The entire memory area, accessible by the processor, is divided into segments, each segment is assigned a corresponding memory block 27

volume, In each case, the segments have a variable size. Memory block 27, in turn, consists of standard memory modules, the inputs / outputs of which are paralleled and connected to the inputs / outputs 30 of device 1. The volume of each block 27 is divided into equal parts — banks of memory 28, and the volume of bank 28 of memory is volume of the memory segment. The memory segment is thus the space through which the processor has access to any bank 28 of block 27. The processor is connected to memory blocks 27 through interfacing devices 1, the function of which is switching the processor channel 26 to blocks 27 at the moment the processor accesses the memory and translates the address from the processor.

Thus, device 1 replaces the high-order bits of the memory address supplied by the processor with the contents of its own, register 4, array number, the value of which is set by the processor in software. Due to the introduction of the interface between the processor and the memory of the device 1, a decoupling occurs between the address coming from the processor and the address entering block 27. As a result, it is possible to increase the number of address bits, and hence the amount of memory blocks ti. At certain points in time, the contents of registers 4 in each device 1 can be different, and the processor gains access to a specific set of banks of 28 memory, with one bank 28 from each block of 27 memory. When the device 1 is turned on, the register 4 of the array number is set to the zero state and the processor has access to the zero banks 28 of each memory block 27. In addition to multi-block memory, the processor may have a memory with a conventional organization, but in this case, the 2 segment decoder must be configured to addresses that are not occupied by the usual memory.

Before exchanging the processor with multi-block memory, the processor needs to set the registers 4 numbers of the required bank numbers to registers 4 in registers 4. For this, the processor sets the address of register 4 to the address bus. Older bits of the address are received over tires 18 to the decoder 3 addresses. The low-order bits of the address go through bus 16 to decoder 3. After that, the processor issues a STR signal to line 25, through which decoder 3 decrypts the address set on buses 16 and 18 and after receiving the RR or PN trunks, respectively, from lines 23 and 24 outputs a single signal to one of the outputs 21 or 22. If decryptor 3 received the signal THU, then from output 21 a single signal goes to the enabling input of node 5, allowing the information recorded on register 4 to pass to bus 12 (processor data). If the decoder 3 received a signal from the processor, the decoder 3 outputs a single signal from output 22 to the decisive input of node 6. After that, the processor sets the required memory bank number to bus 12 and this information. written to register 4. After setting the memory bank numbers on the registers of all 4 devices 1, the processor can access any cell of the installed memory banks. At the same time, the processor does not feel the difference between working with multi-block memory and memory with conventional organization, as the delay on device 1 is determined by the delay on decoder 2, switch 8 and on node 7, which is insignificant and does not violate the channel cycle processor access to memory.

The processor accesses the cell of the memory block 27 as follows. The processor supplies the addresses of the required memory location and the FORM signal to the address bus 16 and 18. Older bits of the address are fed to the information inputs of the decoders 2 of all devices 1. The SIL signal from line 25 is fed to the control input of the decoder 2 of all devices 1. With the arrival of the SIA signal, the decoders 2 decode the higher address bits. The decoder 2, which corresponds to the address set on the tires 18, drives the control signal to the enable input of the switch 8, thereby switching buses 12 and 16 to the selected memory block 27. After the switch 8 triggers, the signal from output 20 goes to the enabling input of node 7, allowing the passing of control signals ZP, THU, SIA corresponding to 5 15 15 25 s

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from lines 23, 24 and 25 to lines 13, 14 and 15 of the same name and further to the control inputs of block 27. In other devices, 1-pass; control signals to the corresponding blocks 27 of memory and commutation of buses 12 (data) and buses 16 mpads of the address of the processor and blocks of memory 27 are prohibited. After that, the processor installs the necessary information on bus 12 (dannk) and sends a signal to the RFP on line 23. At the same time, the information installed on bus 12 (data) and bus 16, the corresponding address bits, goes to pins 11 and 9. through the node 7 to the line 23 PZ and further to the control inputs of the memory unit 27. The signal ZP information, installed on bus 11 (danng), is recorded in the cell of memory block 27, whose address is set on buses 9 and 10.

Thus, the information recorded in register 4 indicates the number of the memory bank 28 in memory block 27, and the address coming from the processor to the lower bits of the address bus indicates the memory location inside the memory bank 28. Similarly, the processor reads information from the memory block 27, but the processor also outputs the signal THU to line 24 and through node 7 to the 24TH line and the control input of the memory unit 27. After this, the memory block 27 sets to the bus 11 the information that the processor reads from its bus 12 (danng).

Thus, the device provides the expansion of the field of application due to a significant increase in the address space of the computing system.

Claims (1)

Invention Formula Device for interfacing processor with multi-block memory, containing register of array number, output and input of which are connected respectively to information input of channel transmitters node and output of first channel receivers node, permitting inputs of which are connected by cell responsibly to first and second outputs of address decoder, first group - .pa whose inputs are connected to a group of control outputs of the processor. and a segment decoder, characterized in that, in order to expand the field of application of devices, a second node of channel receivers and a switch of data buses and lower bits of the address bus are introduced, the information input of the segment decoder and the second group of inputs of the address decoder are connected to the senior bits processor address bus, the third group of inputs of the address decoder is connected to the lower bits of the processor address bus and the first information input of the data bus switch and the lower bits of the address bus, the first output which is connected to the input of the lower bits of the memory address, the second information input and the enable input of the data bus switch and the lower bits of the address bus are connected to the output of the segment decoder, and the second output is connected to the enable input of the second node of channel receivers, the group of inputs of which is connected to the group the control outputs of the processor and the gating input of the segment decoder, and the group of outputs is connected to the group of memory access inputs, the output of the register of the array number is connected to the input of the higher memory address bits, rmatsionny input channel receivers of the first node and the output node channel transmitters connected to a bidirectional data bus and the first processor data input-output data bus switch and low bits of the address bus, a second data input-output of which is connected to the bidirectional bus data memory 1 Editor R. Tsitsika Compiled by V. Vertlib Tehred M. Khodanich Proofreader M. Demchik Order 3092/52 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 FIG. 2