SU1758648A1 - Multiport memory device - Google Patents

Abstract

The invention relates to computing and can be used to build multichannel and multiprocessor computing systems. The invention has focused on reducing the time it takes for the device to access memory. The device contains the first, second and third decoders, from the first to the seventh OR elements, from the first to the ninth And elements, the pulse shaper, the first, second and third delay elements, the drive, the first, second and third D-flip-flops, the constant memory block TI, first, second and third bus drivers, first, second and third Schmidt triggers, switch. The device allows for asynchronous independence of access processes to the individual and common memory sectors of the computing system with fast resolution of access conflicts. 1 ill., 1 tab.

Description

The present invention relates to computing and can be used to build multichannel and multiprocessor computing systems (VS) using some common memory resource.

A device for interfacing computers is known, which contains interface blocks, switches, controller bus seizure units, information buses, controller bus, subscriber adapter blocks, switch service triggers blocks (1). The known device is unnecessarily difficult, has a lot of time and a complicated procedure for accessing data.

The closest in technical essence to the present invention is a multichannel device for data exchange between modules of the computing system, which contains channels 1, ..., (the number of which is equal to the number of air modules). each of which contains four triggers, the first, third and second elements are NOT, the first is the fourth, sixth, fifth, seventh, eighth, eighth elements of AND, the second, first and third elements of OR. the first, third, second and fourth delay elements, two pulse drivers, four AND NOT elements. two blocks of buffer memory, four counters, two comparison schemes, a decoder, a channel polling signal input, a channel polling signal output, information channel input and output, a channel interruption channel request signal output signal, a channel request signal input, a device request line, a device inhibit bus , device gateway bus, device response bus, address bus, devices, device data bus

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va (2). The known device adopted for the prototype.

A disadvantage of the known device is the large transfer time of data from one computer to another, narrow functionality due to the lack of cyclic access priority to avoid collisions, a separate (through computer channels) storage resource, and large hardware redundancy.

The aim of the invention is to reduce the access time to the memory of the device.

The device contains the first 4, the second

5 and third 6 decoders, first to sixth elements OR 13-18, first to ninth elements AND 19-27, pulse shaper 28. first 29, second 30 and third 31 delay elements, drive 36, first 42, second 43 and the third 44 D-triggers, the block of permanent memory 48, the first 49, the second 50 and the third 51 bus drivers, the first 52, the second 53 and the third 54 Schmidt triggers, the seventh element OR 58, the switch 59.

The drawing also shows the first 1, second 2 and third groups of address inputs, the first 7, second 8 and third 9 read inputs, first 32, second 33 and third 34 groups of information inputs - outputs, address inputs of drive 35, information outputs 37 and inputs 38 accumulator, first 39, second 40 and third 41 access inputs, first 45, second 46 and third 47 groups of entries of the address of the memory page, first 55, second 56 and third 57 readiness signals.

The device works as follows. Bus 45, 46 and 47 receives the number (address) of the RAM page in which the device operates. From the outputs of the decoders 4.5 and

6signs of the device address sampling are fed to the inputs of D-flip-flops 42,43 and 44, where they are filtered by the start of the machine cycle signals coming through buses 39, 40 and 41 and are fed to the corresponding address inputs of block 48. The purpose of filtering signals is address sampling quick change of signals on address buses 1, 2 and 3 when changing the current address, especially when the address bus goes to the off state. Pairs of logic elements 13 and 19, 14 and 20, 15 and 21 form a sign of circulation in the write or read memory modes, then these signals go to the corresponding address inputs of block 48. Each of the three lower data bits of block 48 is connected to the input of the trigger node Schmidt is a delay element whose output is connected to the corresponding lower address inputs of block 48, forming a positive asynchronous reverse logical link. Thus, block 48

represents and performs the function of a certain set of combinatorial logic elements and asynchronous triggers, the specific logical functions of which and the electrical connections between them are determined by the firmware table of block 48 (see table).

Bus former 49, 50, and 51 allow two data buses to be formed from bi-directional data buses 32, 33, and 34

5, the information output bus 37 and the information input bus 38. The bus driver is controlled by a combinatorial logic node made on the elements

0 22 27, 16, 17 and 18, to the inputs of which

channel resolution signals from block 48 and memory read signals from the microcomputer are received,

The combination of device addresses is implemented by the switch 59, controlled by the channel resolution signals received from block 48.

The element 58 and the pulse shaper 28 form a recording pulse for accumulators 36.

Consider the simplest case of a single microcomputer to a device in the recording mode of one byte of information in the memory.

5 Bus 7 to the address inputs of the block 48 receives the write signal. If the corresponding calls and records match on the lower (zero) ROM output, the channel 1 resolution signal is generated, which

0 is also fed to the lower (zero) address input of block 48 for storing this event. The channel 1 enable signal in combination with the write signal opens the bus driver 49 in the direction of

5 from the bus 32 data (microcomputer) to the input 38 of the drive. The enable signal of channel 1 also opens switch 59 in the direction from address bus 1 (micro computer) to input 35 (storage device). Logic elements 23,

0 25, 27 and 28 form the recording signal. The pulse shaper 28 forms a recording of a strobe from a long signal into a drive located inside the signal guaranteed to be recorded. Memory reading mode

5 is not fundamentally different from the memory recording mode.

Several microcomputers can be connected to this device (the number of which is not limited in principle). The expansion of the probable conflict situations associated with the temporary imposition of write-read cycles for various microcomputers operating asynchronously takes up a logical node made on the base of the storage unit 48.

In general, the mechanism for resolving conflicts is as follows. When the second (conditional) micro computer is addressed to the device during the start of the write or read cycle of the first micro computer of the second micro computer, the readiness is given a signal not ready on the bus, blocking the second micro computer until the end of the write or read cycle of the first micro computer, after which the second the microcomputer can continue its cycle of writing or reading, provided that during this time (its blocking) a service request was not received from the microcomputer with a high access priority (the access priority rating is included in block 48, otherwise the second microcomputer remains locked until the end of the write or read cycle of the third microcomputer.

If two or more microcomputers are simultaneously accessed, the access permission is issued to the microcomputer with a high level of access priority.

Decoders 4, 5 and 6 and block 48 can be implemented on a microcomputer circuit like 556РТ5, Schmidt triggers 52, 53 and 54 on a chip of type 133ТЛ2, delay elements on any logic element (for example, on a chip 133 ЛИ1), bus drivers 49, 50 and 51 on a microcircuit of type 585VA85, a drive 36 on microcircuits of type 541RU1.

The pulse shaper 28 can be performed on a 133PGZ type microcircuit.

Switch 59 can be performed on three ICs of the 585VA86 type, the corresponding outputs of which are combined, and the enable input of each channel is connected to the pin 11 of the microcircuit.

Technical and economic indicators of the proposed device are provided by reducing the amount of hardware, reducing access time (for a micro computer this device is a transparent part of its own memory), fast resolution of conflicts and unlimited memory size and the number of micro computers connected to this device.

Claims (1)

Claims of the invention Multiport memory device comprising first, second and third decoders, first to sixth OR elements, first to sixth OR elements, first to ninth AND elements, first and second pulse shaper and the third delay elements, the accumulator, the inputs of the first groups of the first, second and third decoders are the corresponding address inputs of the device, the first inputs of the first, second and third elements AND are connected respectively to the outputs of the first, second and third elements OR, characterized in that to reduce the time it takes to 0 device memory, the first, second and third D-triggers, the block of permanent memory, the seventh element OR are entered into it. the first, second and third Schmidt triggers, the first, second and third tire drivers and 5 a switch whose outputs are connected to address accumulator inputs, information inputs and outputs of which are connected respectively to information outputs and information inputs of the first groups of the first, second and third bus drivers, respectively, the information inputs of the second groups of which are the corresponding information inputs-outputs of the device, the information inputs of the first, second and third groups of the switch are connected to the inputs of the first groups of the first, second and third decoders, the inputs of the second whose groups are the corresponding access inputs 0, the device memory page selection, the outputs of the first, second and third decoders are connected respectively to the information inputs of the first, second and third D-flip-flops, the synchronization inputs of which are the corresponding device access inputs, the outputs of the first, second and third D-flip-flops connected to the corresponding address inputs of the fixed memory unit and with the second inputs of the first, second and third elements AND, respectively, whose outputs are connected to the higher address inputs of the fixed memory unit and, the corresponding lower outputs of which connect foam to the inputs of the first, second and third Schmidt triggers, the outputs of which are connected to the inputs of the delay elements, the outputs of which are connected to the corresponding lower address inputs of the permanent memory unit, to the control inputs of the switch and to the first inputs of the elements - combo-I from the fourth to the ninth, respectively, the second inputs of which are connected respectively to the inputs of the first, second 5 and the third OR elements and are the corresponding write and read inputs of the device, the outputs of the fourth, sixth and eighth elements AND are connected to the control inputs of the first, second and third bus driver and the first inputs of the fourth, fifth and sixth elements OR, respectively, the second the inputs of which are connected to the outputs of the fifth, seventh and ninth elements AND respectively, and with the inputs of the seventh element OR, the output of which is connected to the inputs of the pulse former, the output of which is connected to the recording input of opitel, entrance the samples of which are connected to the corresponding output of the fixed memory block, the corresponding outputs of which are the outputs of the device ready signals, the outputs of the fourth, fifth and sixth OR elements are connected to the inputs of the first, second and third bus drivers, respectively. Multiport 3 At the computing system ROM firmware table 123456789 0000 0010 0020 0030 0040 0050 0060 0070 0080 0090 LLP OOSO OODO OOEO wow 0100 0110 0120 0130 0140 0150 0160 0170 0180 0190 01AO 01VO 01SO 01DO 01ЕО 01 GO A B C D E G 10 11 12 13 14 15