SU769620A1 - Buffer storage - Google Patents

Description

And elements, the first inputs of which are connected to the first inputs of the address block. The second inputs of the And elements are connected to the second outputs of the address block, the outputs to one of the inputs of the first counters, the other inputs of which are connected to the third inputs of the address block. The third inputs of the first meters are connected with the first inputs of the second meters and with the second inputs of the address block. The outputs of the first meters are connected to the inputs of the decoders, the outputs of which are connected to the second inputs of the second meters, the third and fourth inputs of which are connected respectively to the second inputs of the And elements and to the second inputs of the first meters. The outputs of the second counters are connected to the first outputs of the address block.

The drawing shows the functional scheme of the proposed memory.

It contains registers, 2i-2 ™ bit switches, control unit 3, sample switch 4, occupancy decoder 5, memory cells 6i-6 "d, address block 7, contains and first counters 8i-8p, second counters 9i -9p, lOi-Ur decoders, elements And lli-lip, 12i-12p sampling, device information inputs, 14n ner output, 15i-15p second outputs, third 16i-16m outputs, recording control bus 17, clock pulse bus 18, read request 19i-19 / i and read enable bus 20.

The device involves block transmission of data from one source to one or more receivers. Each data block is addressed to its receiver. The addressing of the data block is determined by the source by issuing a logic level "1 on bus 12 at the corresponding input of the address block 7 at the time the data block is occupied. The length of the data block can be arbitrary within the scope of the device. Entry of the data block must begin when the corresponding receiver indicator is energized. The repaint is not recorded by the data source, taking into account the status of the busy indicator.

The data is read at the initiative of the receiver, taking into account the state of its indicator, by sending a read request message to the appropriate bus 19. The signal on bus 19 must be maintained until the read permission is received on the corresponding bus 20. Thereafter, the signal on bus 19 must be removed for one cycle on tire 18.

The device works as follows.

In the initial state, the counters, for example, 8i and 9i, and consequently, output 14 are set to the "zero state, and outputs 15 - to" single.

When writing the data word at the ISj-13m inputs, the corresponding code is set, "1" is installed on one of the bus 12s of the nullary receiver, then a write signal is sent to the bus 17. In this case, the code from the 13i-13m buses is written to the lower register li of the device, to the contents the counter 9i of the block 7 of the selected receiver through the open element And lli is set to "1. Counter 9i remains in the "zero state", since at the moment of signal nostuni to the counter input to its input

installation from the output of the IQi decoder comes the level of "O. After the counter 8i has gone to the zero state, the level "O at the output of the decoder lOj disappears and is set to the state"

bus 15i. When the 13i-18m bus receives the next data word from the recording signal from the bus 17, the previously recorded information is shifted by one step towards the higher bits, and the lower data register li is filled with a new data word, and the contents of counters 8 and 9 of the corresponding block 7 is incremented by "1. Thus, the process continues until the signal is removed at

12i-12r tires After that, the source sets the level to "1" on bus 12 of the next receiver and skips the recording of a new data block. The counters 9i-9p of block 7 continue to accumulate “1 for any

to the recording signals, thus saving the start address of its data block, which is shifted towards the higher-order registers of the li-IP device. As new data words arrive, one of the counters

Address unit 7 of the selected receiver sends "1 synchronously to the corresponding counter 9, and the state of the 82-8p counters of other receivers does not change. When reading data, the receiver sends a signal to one of the tires 19i-19 ;; Ziros reading. This signal goes through the control unit 3 by the requests to the corresponding input of the selection switch, and the switch to the control inputs of one of the switches 2i-2m, the outputs of one of the counters 9i-9p of the address block 7. Thus, the next word of the data block is switched to the 16i-16m buses, addressed to the requesting receiver. Data word with

bus 14 is read by the receiver, and the contents of the corresponding counters 9 and 8 of the address block 7 are reduced by "1, and the signal from one of the buses 19 is lowered. The next word reads the same.

Data read by different receivers is carried out in arbitrary order. Reading continues until the corresponding counter 8 goes to

zero state and then zeroed

the corresponding counter 9, and the corresponding ILT is excited, and triggering on one of the outputs 15i-15p of exhaustion of the data block, prohibiting the receiver from requesting data and signaling the source to record a new data block at the address of this receiver.

When a write signal to the bus 17 and a read signal to one of the buses 19 are simultaneously received, the data of the readable register is switched to 16i-16t. The counting inputs of the corresponding counters 9i-9p of the receiver unit 7 selected by the reading board or the counters 9i-9p and 8i -8p, and receiver unit 7, "selected for read and write, is mutually blocked.

The positive effect of using memory is as follows.

The use of memory allows you to organize data transmission from one source to one or more receivers with minimal hardware costs from both the data source and each of the receivers. The number of connected receivers is essentially unlimited.

The memory device allows to organize effective data transmission in systems with different-speed receivers, for example, with receivers with a "floating read cycle" (graphic terminals) due to dynamic memory allocation.

The memory can be successfully used as a high-speed interprocessor buffer in multiprocessor systems with sequential data processing.

The memory device makes it possible to eliminate the influence of the source on the performance of each of the receivers and vice versa due to the possibility of combining the write and read cycles.

The proposed storage device as an interprocessor buffer in a system with one source and one receiver has been used in the “Widescreen Graphic Screen Console of the Designer, A54310, intended for serial production since 1980

The memory for 5 40-bit words was performed on an integrated circuit chip (IC) of an average degree of integration of the K155 series and was tested on an experimental sample A54310.

The implementation of the proposed storage device provides savings due to the reduction in comparison with the prototype equipment for the implementation of storage elements. For every 8 bits of memory, 3 pieces are saved. IMS, i.e. 75 pcs. The IC for each memory device, which, taking into account the cost of manufacturing printed circuit boards, the cost of IC, other materials and assembling blocks of elements, is about 300 rubles.

With a planned production volume of 100 per annum, the annual economic effect will amount to 30 thousand rubles.

Due to the regularity of the memory structure

can be performed on the basis of IC with a high degree of integration.

Claims (2)

1. A buffer storage device containing serially connected registers; the first inputs of the first register are connected to the information inputs of the device; a control unit; an address block read request, write control bus, sampling bus and clock pulse, characterized in that, in order to expand the device's application area and simplify it, bit switches, a sample switch and a descrambler are entered, the inputs of which are connected to the first outputs of the address block and the first inputs of the sample switch, the output of the busy decoder is connected to the first output of the device, the second outputs of the switch switch are connected to the outputs of the control unit whose inputs are connected a read request buses, address unit first inputs connected to the sampling schinam second input - to the bus clock, the third input - to the output control unit outputs the second address unit connected to the second register inputs and record management control; third outputs — with the second outputs of the device; outputs of the registers are connected to one of the inputs of the bit switches, the other inputs of which are connected to the outputs of the select switch, the outputs of the bit switches are connected with the third outputs of the device. 2. Device for and. 1, characterized in that the address block contains counters, decryptors and elements, the first inputs of which are connected to the first inputs of the address block, the second inputs of elements AND are connected to the second output m of the address block, outputs of the elements And are connected to one of the inputs of the first meters, the other inputs of which are connected to the third inputs of the address block, the third inputs of the first meters connected to the first inputs of the second meters and the second inputs the address block, the outputs of the first counters are connected to the inputs of the deschiftorators, the outputs of which are connected to the second inputs of the second counters, the third and fourth inputs of which are connected respectively to the second inputs of the elements And with the second inputs of the first counters, the outputs of the second counter connected to the first outputs of the address block. Information sources, taken into account in the examination 1. Express-information series “Computing Technique, No. 26, 1978. 2. USSR author's certificate number 519761, cl. G PS 19/00, 07.05.74 (prototype). G / L G / L I I G11, 3 / J / l ABOUT tr5d-b /9, / 7 / S t2i i