SU1300489A1 - Device for providing parallel access to common memory - Google Patents

Abstract

The invention relates to computing and can be used to interface digital computers in systems. The invention solves the problem of increasing the speed of the device by providing simultaneous reading of several blocks of memory 1 from several cells. This task is solved by converting the addresses of the memory cells into a unitary code on the address conversion block 4, followed by independent access to several cells of block 1, which are registers controlled by synchronous inputs. 3 hp f-ly, 6 ill. 8 e (L of about CX) with

Description

The invention relates to computing and can be used in digital computers and systems.

The aim of the invention is to increase the speed of the device by providing simultaneous reading from - several cells of the memory block.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - functional diagram of the first switch; in fig. 3 - the same, the second switch; in fig. 4 - the same, the memory block; in fig. 5 - the same, address translation block; in fig. 6 - key scheme is functional

The device comprises a memory block 1, two switches (block) 2 and 3, and an address translation block 4.

The device has address 5, information 6 inputs, inputs 7 of the write signals, inputs 8 of the i-read signals and information 9 outputs,

Memory block 1 contains registers 10 and has information inputs 11, synchronous inputs 12 and information outputs d1 13.

The first switch 2 contains the input element OR 14, the group of elements And 15,

a group of keys 16, M groups by N subgroups of output elements AND 17 and M groups by N output elements OR 18

The first switch 2 has the second information inputs 19, the control inputs 20, the outputs 21 of the second group, the first information inputs 22, the outputs 23 of the first group.

The second switch 3 contains M switching nodes 24, each of which contains N groups of 25 AND elements and N elements OR 26, and also has strategic inputs 27, control inputs 28, information inputs 29 and outputs 30.

The address translation unit 4 comprises M decoders 31 and has inputs 32 and outputs 33.

The key 16 of the group contains M input elements AND-NOT 34, output element AND-NOT 35 and has inputs 36 and output 37.

The principle of operation of the device is based on the independence, simultaneous access of several processors to the same memory cell when reading and to different memory cells when writing. This is achieved by

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blocks 2 and 3. When writing to the inputs 32 of block 4, the address of the cell arrives, to inputs 22 — information that needs to be recorded; to inputs 19 — recording signals. If at block 12 the address of the same memory cell comes from different processors at the same time, then the recording in block 1 does not occur, and a record is possible in different memory cells. When reading, block 2 provides simultaneous reading of information by different processors from the same memory cell. At the inputs 28 of the unit 3, the address-to the inputs 27 is received — read signals; the information read from the outputs 30 via the information buses enters the processors.

The device works as follows.

When recording information, the address of the cell with a parallel binary code goes to block 4, where it is converted into a unitary binary code and comes from the outputs 33 of block 4 to the inputs 20 of block 2. The recording signals go to the inputs 19 of block 2, the information that needs to be written is fed to the inputs 22 block 2. In block 2 (Fig. 3), the cell address is fed to the inputs of the keys 16, the number of which is equal to the number of memory cells. If the input of the same key 16 receives the address of the cell from different processors, then there will be no signal at the key output. If a cell is accessed by a single processor, then at the output of key 16 a signal appears that goes to the first group of elements AND 15 to the element of the corresponding cell. At the second input element And 15 receives a signal

recording from the output of the OR 14 element, as a result of which, at the output of the corresponding element AND 15, a signal appears that goes to the syncro input of the memory block cell. The signal from the output of the key 16 also enters the first groups of elements AND 17, the second inputs of which receive the information that needs to be recorded. Information on the recording goes to all elements AND 17, if there is a signal from key 16 at the inputs of a subgroup of elements AND 17 from the information through elements AND 17 of the corresponding processor, it enters the inputs of the elements OR 18 and then from the outputs 23 of block 24 enters the inputs 11 of block 1.

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Reading information. Simultaneous reading of information will be provided by block 3. In block 3, the group of elements AND 25 can be divided into subgroups the number of elements AND 25 in each subgroup is equal to the number of memory cells multiplied by the cell width. When reading information, the cell address comes from the outputs 33 of block 4 to the inputs 28 of those elements And 25 that relate to that cell whose address is determined by block 4. Information goes to the inputs 29 of those elements 25 of Block 3 that relate to the cell, with which information is read. Information is read from the subgroup of elements AND 25, to the input 27 of which a read signal is received. In the presence at the inputs of elements AND 25 of the signal from the outputs 33 of block 4, from the outputs 13 of block 1 of information, the elements OR 26 pass through the information buses from the outputs 30 of block 3, to the output of the device.

Claims (4)

Formula invented and 1. Device for parallel a shared memory access containing 30 ladies of elements AND groups, second inputs a memory unit, two switches and an address translation unit whose inputs are the corresponding address inputs of the device, and the outputs are connected to the corresponding control inputs of the first switch, in order to improve the speed of the device by simultaneously reading several cells of the memory unit, the first information inputs of the first switch are the corresponding information inputs of the device, the second information inputs of the first switch are corresponding By the existing recording signal inputs of the device, the control inputs of the second switch are connected to the corresponding control inputs of the first switch, the outputs of the first group of which are connected to the corresponding information inputs of the memory block, the outputs of the second group of the first switch are connected to the corresponding synchronous inputs of the memory block whose information outputs connected to the corresponding informational input 40 which are connected to the outputs of the corresponding group keys whose inputs are the corresponding control inputs of the first switch, The 35 outputs of the AND group elements are the corresponding outputs of the second group of the first switch, the output of the i-ro key (, ..., M) is connected to the first inputs of the output elements AND of all N subgroups of the i-th group, the second input of the i-ro element I 1 th sub-ruby (1 1, ..., N) of all M groups is the 1st bit i-ro of the first information input of the first switch, the outputs of the output elements AND the 1st subgroup of the i-th group are connected to the corresponding inputs of 1- th output element OR of the i-th group, the output of which is the 1st bit of the i-ro output of the first group of the second switch, 4. A device according to claim 1, characterized in that the second switch comprises. M switching nodes 55 each of which contains N groups of elements AND IR of elements OR, with the first inputs of elements AND of the i-ro group of the switching node connected to the i-th 45 50 I will give the second switch, CIC) the coaxial inputs of which are the corresponding inputs of the signal read by the device, and the information outputs are the corresponding information outputs of the device. 2. The device according to claim 1, characterized in that the memory block is made on registers, the information input, the sync input and the output of each register being the corresponding information input, the sync input and the information output of the memory block. 3. The device according to claim 1, which is based on the fact that the first switchboard contains an input element OR, a group of elements AND, a group of keys, M groups of N subgroups of output And (where M is the number of information inputs (outputs) of the first switch, N is the number of binary bits, information input (output)) and M groups of N are output OR elements, and the inputs of the input element OR are the corresponding second information inputs the first switch, the output of the input element OR is connected to the first input which are connected to the outputs of the corresponding group keys whose inputs are the corresponding control inputs of the first switch, The 5 outputs of the AND groups are the corresponding outputs of the second group of the first switch, the output of the i-ro key (, ..., M) is connected to the first inputs of the output elements AND of all N subgroups of the i-th group, the second input of the i-ro element I 1 th sub-ruby (1 1, ..., N) of all M groups is the 1st bit i-ro of the first information input of the first switch, the outputs of the output elements AND the 1st subgroup of the i-th group are connected to the corresponding inputs of 1- th output element OR of the i-th group, the output of which is the 1st bit of the i-ro output of the first group of the second switch, 4. A device according to claim 1, characterized in that the second switch comprises. M switching nodes 5 each of which contains N groups of elements AND IR of elements OR, and the first inputs of elements AND of the i-ro group of the switching node are connected to the i-th five 0 gating input of the second switch, the second inputs j-x (j 1,.,., Z) of elements And groups of i-ro node switching is connected to the j-th bit of the i-ro control input of the second switch, the second inputs of the elements And groups of the i-ro switching node form the corresponding bits of the i-ro inforpp 1112 1112 R S / J 13 the output of the second switch, the outputs of the elements AND of the 1st group of the i-ro switching node are connected to the corresponding inputs of the 1st OR element of the same switching node, the output of which is the 1st bit of the i-ro information output of the second switch. mr L 13 / J FIG. i-j 27 29 28 32 32 33 1300489 27 Fig4 32 33 of FIG. five .33 Editor M. Kelemesh Compiled by N. Zakharevich Tehred M. Khodanich Proofreader T. Kolb Order 1151/49 Circulation 673 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 35 37 FIG. 6 Subscription