SU1432538A1 - Device for interfacing processor with multimodule storage - Google Patents

Abstract

The invention relates to a computing technique and can be used to increase the amount of RAM in the construction of a number of "mini- and microcomputer-based systems." The purpose of the invention is to expand the functionality by organizing work with memory segments. - arbitrary volume and arbitrary location within the address space of the processor. In the device containing the first register 4 numbers of the array, the decoder 3 addresses, the decoder 2 segments, nodes 11-13 channel receivers and transmitters of communication with the processor and memory unit, switch 10 data buses and low-order bits, entered 7 numbers segment, specifying the location of the segment in the address space of the processor, the second register 5 of the array number, allowing to increase the number of address bits of the memory block, mask register 6, specifying the segment volume, two groups of elements 8 and 9 that mask the corresponding enno mpadshie and older bits of the processor address bus, components 14-19,-channel transmitters and receivers communicate with the processor. The segment size can vary from one word to the entire address space of the processor. 1 il. ) (L 4i SO oo 00 00

Description

The invention relates to computing: Telnaya technique and can be Kcnojib-; 3ovio to increase the amount of RAM in the construction of computer systems based on mini and microcomputers

The purpose of the invention is to expand the functional: rational capabilities by providing the opportunity to work with the segment: Tami memory of arbitrary size and arbitrary QC allocation within the limits of the address space of the processor; The drawing shows the block diagram of the device

I Device 1 contains a decoder 2 segment, a decoder 3 addresses, the first A and the second 5 registers of the array number, | register 6 masks register 7 segment numbers, groups 8 and 9 of the Ir elements 10 bus data and low busbar addresses node 11 channel Receivers, nodes 12-19 channel with mixers and transmitters of communication with the process;; oor, channel 20 processord, block 21 there, line 22 of signal Recording RFP), line 23 of signal read (THU) TC line 24 of signal Synchronization of the ad- (force) p of the group of control inputs 25 and the corresponding line 6-28 of the group of outputs of the signals (1 and to memory block 21, the inputs of the first register 4 of the array number are connected by the codes of the node of 13-channel receivers, and the outputs are connected to the older bits of the bus 29 of the address of the memory block 21 and t information inputs of the node 12 transmitters, inputs of the second register 5 of the array number are connected to the U outputs of the node 14 channel receivers, and outputs to information nodes of the 15 channel transmitters and to the direct inputs 30 of the first group of 8 elements AND whose outputs are connected to the bus 31 of the address of memory block 21 , the inputs of the register 6 of the mask are connected to the output 16 channel receivers are evil, and the outputs are with the information inputs of the node 17 channel transmitters, the inverted inputs 32 of the first group of 8 And elements, the first "moves 33 of the second group of 9 And elements, and the inputs 34 of the decoder of the 2 segments, the inputs of the 7 segment number are connected to the outputs of the node 18 channel receivers, and the outputs - with the information inputs of the node 19 of the channel transmitters and with the inputs 35 of the depot 2 segments, the inputs 36 of which are connected to the bus 37 of the address

five

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five

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five

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pa, information inputs of the address decoder 3 and second inputs 38 of the second group of 9 elements And whose outputs are connected to inputs 39 of switch 10, outputs 40 of which are connected to the lower bits of the bus 41 of address 21 of the memory block 21, information inputs of nodes 13, 14, 16 and 18 channel receivers and outputs of nodes 12, 15, 17, and 19 of transmitter tapes are connected to a bi-directional bus 42 of the processor and to the first inputs-outputs of the switch 10, the second inputs-outputs of which are connected to the bi-directional bus 43 of the memory block 21, lines 22-24 are connected with the control inputs of the address decoder 3, the SIL line 24 is connected to the control input 44 of the decoder 2 segment, the output 45 of which is connected to the information 46 and the enabling 47 inputs of the switch 10, the information output 48 of which is connected to the enabling input of the 11 channel node receivers, outputs 49-56 of the address decoder 3 are connected respectively with the inputs of nodes 12-19 of channel receivers and transmitters about

The device works as follows.

The format of the second register 5 of the array number, register 6 of the mask and register 7 of the segment number coincides with the format of the address word of the processor, i.e. the number of bits of these registers is equal to the number of address spaces of the processor. The maximum capacity of each memory block 21 can be no more than 2 V words, where N1 and N2 are the number of bits of the first 4 and second 5 registers of the array number, respectively. Mask register 6 is used to set the size of the memory segment. The format of mask register 6 is the same as the format of the address word of the processor, which allows the memory segment to vary in size from 1 to 2 words. The location of the segment in the address space of the processor is determined by the contents of register 7 of the segment number. The memory segment thus occupies a part of the address space of the processor, through which the processor has access to the equal-sized array of the memory block 21, the number of which is determined by the value of the first 4 and second 5 registers of the array number. The processor is connected to the memory block i and 21 through special interface devices 1, the functions of which are switching the processor channel 20 with the memory blocks 21 at the time the processor accesses the memory and converts the address received from the processor.

Thus, device 1 replaces the higher bits of the memory address provided by the processor with the contents of the first 4 and second 5 registers of the array number, the value of which is set by the processor programmatically. At certain times, the contents of registers 4-7 in device 1 can be different and the processor gets access to any array of memory blocks 21, but one array from each block 21, and the volumes of the arrays, their numbers and the location of the corresponding segments can be arbitrary and change the program INR is in the process of resolution of the problem. In addition to the multi-block memory, the processor can have memory with the usual organization, but in this case the register 7 segment number and the mask register 6 must be configured so that if you use the signal THU, then the single signal comes from output 49 on resolving input node 12, allowing the passage of information recorded on register 4, on the bus 42 data processor. In the Record mode, the processor after the PIA signal sets the required value of the high-order bits of the array number to bus 42 and generates an RFP signal, via which the decoder 3 outputs a single signal from the output 50 to the enable input of node 13, and informatd from the processor data bus 42 is written to register 4o Reading and writing to registers 5-7 is done in a similar way. After installing the memory array numbers on registers 4 and 5, the volume of segments on registers 6, and segment numbers on registers 7 of all devices 1, the processor can access any cell of the installed arrays of memory blocks 21. It should be noted that in this case, the processor does not feel the difference between working with multi-block memory and memory with the usual organization, since the delay on the device 1 is determined by the delay.

addresses that were not used by JQ pe 2, switch 10 and node 11,

Noah memory. At the moment device 1 is turned on, the first 4 and second 5 registers of the array number, the mask register 6 and the register 7 segment numbers are set to the zero state and the processor is insignificant and does not violate the channel cycle of the processor memory access

The processor accesses the memory cell 1 of the memory.

the sor through the zero cell of the memory has 5. The processor feeds on the tires 37

access to the zero cell of each block

21 memories.

I

Before exchanging the processor with multi-block memory, the processor needs to set the first 4 and second 5 registers of the array number in the first 4 and second 5 registers of the array to the number of required arrays of blocks 21, on the mask registers 6 the required segment volumes and on registers 7 to the number of memory segments. For this, the processor places the address of the first 4 register of the array number on the address bus. Address bus 37 is supplied to the information inputs of the decoder 3 addresses. After that, the processor feeds the SIA signal to line 24, via which the decoder 3 decrypts the address set on address buses 37 and, after receiving control signals ZP or THU, respectively, from lines 22 and 23, sends a single signal to one of outputs 49-56.

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45

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the address is the address of the required memory cell and generates a BIA signal. This address is fed to the inputs 36 of the decoders for 2 segments of all devices 1. The SIA signal from line 24 is fed to the control input 44 of the decoders of 2 devices 1. With the arrival of the signal SIA, the 2 bits of the address received from the bus 37 of the processor's address with the high bits of the register 7, the number of the segment, which is fed to the inputs 3 of the decoder 2. The number of old numbers of rows is determined by the contents of the register 6 of the mask, whose codes are connected to the inputs 34 of the decoder 2 and mask the lower bits of the address of the register of the segment number .

If the high-order bits of the address match, the decoder 2 generates a control signal, which from output 45 enters the information 46 and resolves 47 inputs of the switch 10

which is insignificant and does not violate the channel cycle of the processor accessing the memory

The processor accesses the cell of the memory block 1 and a trace occurs. The processor feeds on the tires 37

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the address is the address of the required memory cell and generates a BIA signal. This address is fed to the inputs 36 of the decoders 2 segments of all devices 1. The SIA signal from line 24 goes to the control input 44 of the decoders of 2 all devices 1. With the arrival of the signal of the SIA, the 2 segments of the address are compared with the addresses of the processor the higher bits of register 7 are the segment numbers that arrive at inputs 35 of the decoder 2. The number of old bits is determined by the contents of register 6 of the mask, whose codes are connected to the inputs 34 of the decoder 2 and mask the lower bits of the register address 7 but EPA segment.

If the high-order bits of the address match, then the decoder 2 generates a control signal, which from output 45 enters information 46 and resolves 47 inputs of switch 10,

thus, 42 data and the lower bits of the address are correspondingly allocated to 43 and 41 of the selected memory block 21. Register 6 masks using the first 8 and second 9 groups of elements And masks respectively; the lower bits of the second 5 register of the array number and the higher bits of the bus: we have 37 processor addresses After the input from the first channel transmitting node of the switch goes 10 the output signal 48 arrives at the permitting input of node 11, allowing the passage of the L signal signals of the RF, TH, SIL, respectively, with lines 22, 23 and 24 to one 15

The inputs for the first channel receivers node and the first channel transmitters node are connected to the first and second outputs of the address decoder, the output of the first register of the array number is connected to the output of the higher device address memory bits, the information input of the first channel receiver node the transmitters are connected to the input-output data bus of the processor of the device and the first information input-output of the data bus switch and lower bits

The nominal lines 26, .27 and 28 and later are the control inputs of the memory block 21, the rest of the devices: 1 passing the control signals to the corresponding two sound blocks 21 of the memory and switching | of the data buses 42 and the PN 39 mps; The addresses of the processor and blocks of 21 units are prohibited.

 After that, the processor installs the necessary information on the bus 42 data and sends a signal to the line 22 | 1, this information, which is set by jia to the data bus 42 and the inputs 39 for the address numbers, goes to the bus 43 I 41. node 11 to line 26 and further to the inputs of the control of memory block 21. According to the signal Sn, the information set on data bus 43 is recorded in the cell of memory block 21, whose address is set on buses 29, 31 and 41. The information recorded in the first 4 and second 5 registers of the array number indicates block 21 of memory, $. the address coming from the liia processor minus bits of the address 41 bus indicates the address of the memory cell inside the array of block 21. Similarly, the processor reads information from memory block 21 but the processor issues a THU signal to line 23 and through node 11 to line 27 and a control input of the memory unit 21. After that, the memory unit 21 sets the bus 43 with the information that the processor retrieves 42 data from its bus.

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The gates that allow the inputs of the first node of channel receivers and the first node of channel transmitters are connected respectively to the first and second outputs of the address decoder, the output of the first register of the array number is connected to the output of the higher bits of the device memory address, the information input of the first node of channel receivers and the output of the first node channel transmitters are connected to the input / output of the data bus of the processor of the device and the first information input / output of the data bus switch and lower bits

25 address bus, the second information input-output of which is connected to the output of the device’s data bus, the control inputs of the device are connected to the inputs of the first group of the address decoder, the gate input of the segment decoder and the inputs of the group of the second node of channel receivers, the outputs of which are connected to access outputs device memory, the output of the segment decoder is connected to the first information and enable inputs of the data bus switch and the lower bits of the address bus, the first output of which is connected to the enable the second output of the channel receivers, and the second output - with the output of the lower bits of the device’s memory address, which is so that, in order to expand the functional capabilities of jgs by organizing work with memory segments of arbitrary size and arbitrary location within the address space of the process30

ZB

4D

pa, it entered the second register

formula of invention

gQ array numbers, mask register, segment number register, second, third, and fourth nodes of channel transmitters, third, fourth, and fifth nodes of channel receivers, first eg, and second group of AND elements, output

A device for interfacing a third node channel receivers with a multi-block memory j is connected to the information input on the second register of the array number, the decryption register of the array number, the output of the address decoder, the segment decoder, which is connected to the information

the first node of the channel transmitters, the first and second nodes of the channel receiver, the data bus switch and the lower bits of the address bus, the input of the first register of the array number is connected to the output of the first node of the channel receivers, the output of the first register of the array number is connected to the information

the input of the first node of the channel transmitters

The inputs for the first channel receivers node and the first channel transmitters node are connected to the first and second outputs of the address decoder, the output of the first register of the array number is connected to the output of the higher device address memory bits, the information input of the first channel receiver node the transmitters are connected to the input-output data bus of the processor of the device and the first information input-output of the data bus switch and lower bits

address bus, the second information input-output of which is connected to the device’s data bus output, the device’s control inputs are connected to the addresses of the first group of the address decoder, the gate of the segment decoder and the inputs of the group of the second channel receiver node, the outputs of which are connected to the memory access outputs device, the output of the segment decoder is connected to the first information and enable inputs of the data bus switch and the lower bits of the address bus, the first output of which is connected to ode of the second node of the channel receivers, and the second output - with the release of the lower bits of the device’s memory address, as indicated by the fact that, in order to extend the functionality by organizing work with memory segments of arbitrary size and arbitrary location within process address space

pa, it entered the second register

714325388

the input of the second node of the channel circuits on the inputs of the second group of deganfrac sensors and the direct inputs of the segment torus elements, the inputs of the third group AND of the first group, whose outputs are connected to the bus inputs to the outputs of the address bus of the device’s address, input - the device, code of the fourth node of the second group of the decoder of the address of the nal receivers is connected to the information and second inputs of the elements AND the second matsyonny input of the mask register, vygluy, permitting the inputs of the third, which moves are connected to the bit The fourth and fifth nodes of the channel information input of the third node Q receivers are connected respectively to the channel transmitters, the inputs of the first, third, and fifth output groups of the segment decoder, and the address decoder permitting the top inputs of the AND elements of the first inputs of the second, the third and fourth groups and the first and the inputs of the elements AND nodes of the channel transmitters of the second group, the outputs of which are connected, respectively, with the sixth, seventh and second bits of the informational and eighth outputs the encryption input of the data bus switch and the address, the information inputs of the third-lowest bits of the address bus, its output, the fourth and fifth nodes of the link node of the channel receivers of the receivers, and the outputs of the second, are the same as the information input of the second-third and the fourth channel nodes, the segment numbers, the outputs of which transmitters are connected to the input, are connected to the information inputs by the data bus output of the processor of the fourth node of the channel transmitters.

Claims (1)

Claim A device for interfacing a processor with multi-block memory, containing the first register of the array number, the address decoder, the segment decoder, the first channel transmitter node, the first and second channel receiver nodes, the data bus and low-order bits of the address bus, the input of the first register of the array number is connected to the output the first node of the channel receivers, the output of the first register of the array number is connected to the information input of the first node of the channel transmitters, allowing the inputs of the first node of the channel receivers and the first the channel transmitter node are connected respectively to the first and second outputs of the address decoder, the output of the first register of the array number is connected to the high-order output of the device memory address, the information input of the first channel receiver node and the output of the first channel transmitter node are connected to the input / output of the device processor data bus and the first information input-output of the data bus switch and the least significant bits of the address bus, the second information input-output of which is connected to the output of the memory data bus devices, the control inputs of the device are connected to the inputs of the first group of the address decoder, the gating input of the segment decoder and the group inputs of the second channel receiver node, the outputs of which are connected to the memory access outputs of the device, the segment decoder output is connected to the first information and enable inputs of the data bus switch and lower bits of the address bus, the first output of which is connected to the enable input of the second node of the channel receivers, and the second output - with the output of the least significant bits of the memory address devices, which means that, in order to expand functionality by organizing work with memory segments of arbitrary volume and arbitrary location within the address space of the processor, a second array number register, mask register, segment number register, second are entered into it the third and fourth nodes of channel transmitters, the third, fourth and fifth nodes of channel receivers, the first and second groups of elements And, the output of the third node of channel receivers is connected to the information input of the second an array number register, the output of which is connected to the information input of the second node of the channel transmitters and the direct inputs of the elements And of the first group, the outputs of which are connected to the outputs of the device memory address bus, the output of the fourth node of the channel receivers is connected to the information input of the mask register, the outputs of which are connected to the bits of the information the input of the third node of the channel transmitters, the inputs of the first group of the segment decoder, the inverse inputs of the elements And the first group and the first inputs of the elements And the second groups whose outputs are connected to the bits of the second information input of the data bus switch and the lower bits of the address bus, the output of the fifth node of the channel receivers is connected to the information input of the segment number register, the outputs of which are connected to the information inputs of the fourth node of the channel transmitters and the inputs of the second group of the segment decoder, the inputs of the third group of which are connected to the inputs of the address bus of the processor of the device, the inputs of the second group of the address decoder and the second inputs of the elements AND of the second group, the resolving inputs of the third, fourth and fifth nodes of the channel receivers are connected respectively to the third, fourth and fifth outputs of the address decoder, allowing the inputs of the second, third and fourth nodes of the channel transmitters connected to the sixth, seventh and eighth outputs of the address decoder, information inputs of the third, fourth and the fifth nodes of the channel receivers and the outputs of the second, 2θ of the third and fourth nodes of the channel transmitters are connected to the input of the output of the data bus of the processor of the device.