RU2014732C1 - Multichannel commutator - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: multichannel commutator has M asynchronous channels incorporating recording-reading commutator, address commutator, instruction commutator. It implements communication between several computers over four communication lines and between computers and outside reading and recording devices over three communication lines. Number of switched computers equals number of asynchronous channels of commutator. EFFECT: increased speed of information exchange. 4 cl, 2 dwg

Description

 The invention relates to computer technology and can be used in information exchange systems, the results of counting between several computers and external devices.

 A device for the exchange of information containing a synchronization unit, the outputs of which are connected to the first inputs of the blocks for connecting serial channels, a priority block, a buffer memory block, a block of channel register nodes, a free zone search unit, a time unit and a control unit connected by a group of inputs and outputs respectively, with the inputs and outputs of the buffer memory, the block of nodes of the channel registers, the block for searching for free zones, the block of time counting, the block for connecting serial channels, and blocks parallel channels and the output of the priority block, the request inputs of which are connected to the output of the time unit, the outputs of the serial and parallel channels connected by information inputs and outputs to the inputs and outputs of the block of channel recording nodes, which is connected by two-way connections to the free zone search block and the buffer block memory [1].

 The disadvantage of this device is the limited scope due to the fact that the device does not provide operational transmission of a computer connected to one of the parallel channels of the exchange device, information in accordance with its priority and information consisting of several messages. In addition, the time of occupation of the zone is rigidly fixed, and this leads to the need to frequently repeat the input of messages into computers.

 The closest in technical essence to the proposed device is a multi-channel switch containing communication lines, each of which is connected to the first input of the corresponding transceiver unit, demultiplexer, first multiplexer, counter, generator, comparison unit, spatial switch, M additional multiplexers, M information exchange units , analysis unit, address switch, M registers, key registration control unit, M display units [2].

 The disadvantage of this switch is the low speed of information exchange and the low speed of the switch due to the synchronous operation mode of the device blocks.

 The purpose of the invention is to increase the speed of information exchange.

 This is achieved through the use of the asynchronous mode of operation of the switch and the possibility of independent exchange between multiple devices.

 In FIG. 1 shows a functional diagram of the proposed switch; in FIG. 2 is a schematic diagram of an asynchronous switching channel.

 The switch contains M asynchronous channels (1 ... M) connected by a bulk patch board (see Fig. 1). Each asynchronous channel contains a command switch 1, an address switch 2, a write-read switch 3, a key block 4 (on I elements), a common volume patch board 5, external input-output buses 6-21, external buses 22-37 readouts, external write buses 38-53, communication lines 54-57 of bus 6 of the first channel with board 5, communication lines 58-60 of bus 22 of the first channel with board 5, communication lines 61-63 of bus 37 of the Mth channel with board 5, communication lines 64-66 of the bus 38 of the first channel with the board 5, communication lines 67-69 of the bus 58 of the Mth channel with the board 5, bi-directional command line 70 of the first channel 1 switch with the first channel address switch 2, the communication line 71 from the first channel command switch 1 to the first channel switch 3, the bi-directional communication line 72 of the first channel switch 1 with the key block on the And elements of the first channel, the communication line 73 from switch 3 the first channel to the key block 4 of the first channel, the communication line 74-79 from the switch 2 of the first channel to the key block 4 of the first channel, bidirectional communication lines 80-85 of the key block 4 of the first channel with board 5, the bi-directional communication line 86 torus of channel 1 of the Mth channel with a switch of Channel 2 of the Channel M, communication line 87 from the switch of Channel 1 of the Channel M to the switch 3 of Channel M of the switch 3 of Channel M of the channel, a bi-directional communication line 88 of the switch of Channel 1 of the a key block of the 4th Mth channel, a communication line 89 from the switch of the 3rd Mth channel to a key block of the 4th Mth channel, a communication line 90-95 from the switch 2 of the Mth channel to the key block of the 4th Mth channel, bidirectional lines 96-101 communication key block 4 of the Mth channel with the board 5, communication lines 102-105 of the bus 21 of the Mth channel with the board 5, communication lines 106 and 107 of the switches 2 and 3.

 External input devices, such as computers, can be connected to external input-output buses 6-21, external reading devices to external reading buses 22-37, and external recording devices to external writing buses 38-53. External devices communicate with each other, with external readers and with external recording devices using a switch.

 The design of the proposed switch depending on the element base can be different. An example of the execution of the circuit of one channel of the switch for communication of 16 external devices, 16 external reading devices and 16 external recording devices is shown in FIG. 2.

 The switch operates as follows.

 The initial state of each channel of the switch is as follows (see Fig. 1): in the communication lines 54-57, 102-105, 58-69 - "log. 0". The switch is configured to receive an external signal.

 On the first line 54 or 102 of the input-output bus (6-21), a transfer request is received or a request is sent; on the second line 55 or 103 of the input-output bus (6-21), a signal of readiness for exchange is received and a signal of readiness is sent; on the third line 56 or 105 of the input-output bus (6-21), an information signal is transmitted; on the fourth line 57 or 105 of the input-output bus (6-21), the input-output bus is exchanged via board 5 with key block 4 and switches 1, 3, and 2.

 Input-output buses 6-21, read buses 22-37 and write buses 38-53 of each channel are connected through a board 5 to the key unit 4 and the switches 1, 3 and 2 of the corresponding channel.

 On the 57th or 105th communication line of the bus 6 or 21, a request for permission to exchange is received in the form of "log. 1" and at the same time on the 56th or 104th communication line of the bus 6 or 21 there is a request for recording to another input output bus 7-21 or to the bus 38-53 records in the form of "log. 1". If “log. 1” does not arrive on the 56th or 104th communication line, then a request is made to read from bus 7-21 or from bus 22-37. In the 55th or 103rd communication line remains "log. 0". The switch channel is configured to read.

 On the second output of the address switch 2 of the corresponding channel, “log. 1” appears and goes to the seventh input of the address switch 2, on the eleventh output of the command switch appears “log. 1” and goes to the eighth input of the switch 1, on the fifteenth output of the switch 1 appears “log . 1 ", then" log. 1 "appears on the first output of switch 3, which switches the mode switch to recording mode:" log. 1 "is set on the seventh output of switch 3, and" log. 0 "is on the eighth output.

 From the third output of switch 3, “log. 1” is sent to the fifteenth input of switch 1, at the twelfth output of switch 1, “log. 1” is received, which goes to the twelfth input of switch 1. As a result, “log. 1” is formed on the sixteenth output of switch 1 at the second output of switch 1, a “log. 1” is obtained, going to the 55th or 103rd communication line of bus 6 (7-21), which is a signal that the switch channel is ready to receive the address of the channel with which it is necessary to establish communication.

 On the 56th or 104th communication line of bus 6 (7-21) a series of pulses arrives, according to the number corresponding to the channel number through which buses communication is established. The pulses go to the second input of switch 1, from the first output of the command switch, go to the seventh input of the switch 1, from the fourth output of the command switch, the pulses go to the fifth input of the address switch, on the third, fourth, fifth, sixth outputs of which the state corresponding to the number of the connected channel is formed , which is decrypted by the address switch 2. As a result, "log. 1" appears on the corresponding output of the address switch (seventh, ..., (M + 7)), the corresponding numbers are connected the channel unit 4 keys, and the channel is ready for communication buses interconnected pairwise 6-21 or 38-53 with the tires on the record.

 Similarly, there is a connection of tires 6-21 with each other in pairs or with tires 22-37 for reading.

 Thus, the proposed multi-channel switch provides an increase in the speed of information exchange due to the possibility of an independent conventional between several channels simultaneously.

Claims (4)

 1. MULTI-CHANNEL SWITCH containing communication lines, each channel of which contains an address switch made on a counter, the output of which is connected to the input of the decoder, command switch, a key unit, characterized in that a common volume patch card is connected, which is connected to the input-output buses , with write and read buses, with inputs and outputs of the key block of each channel, respectively, a write-read mode switch is inserted into each channel, the inputs of which are connected to the outputs of the command switch ra and the outputs of the address switch, and the outputs are with the inputs of the key block, respectively, with the inputs and outputs of the command switch connected to the inputs and outputs of the address switch and the inputs and outputs of the key block, respectively, the outputs of the address switch with the inputs of the key block of the corresponding channel.  2. The switch according to claim 1, characterized in that the command switch contains four AND elements, five NOT elements, a counter and a decoder, the first input of the first And element being the first input of the command switch and connected to the second input of the second And element, which is the fourth input command switch, with the first input of the first element NOT, which is the ninth input of the command switch, and is the fourth input of the address switch and the output of the fourth communication line input-output bus, the second input of the first element And I is the second input of the command switch and the output of the third communication line of the input-output bus and the (4M + 4k + 3) -th output of the key block, where k = 0,1, ..., M, M is the number of channels, as well as (4k +3) -th input of the key block, the output of the first AND element is the first output of the command switch and connected to the first input of the fourth AND element, which is the seventh input of the command switch, with the input of the third element NOT and is the second input of the Write-Read mode switch, the first input of the second element And is connected to the second input of the fourth element , with the third output of the decoder and is the sixteenth output and the third input of the command switch, the second output of the second element And is the second output of the command switch, the output of the second communication line of the input-output bus, (4M + 4k + 4) = m output of the key block, where k = 0,1, ..., M, M is the number of channels, the first input of the third AND element is connected to the second output of the decoder and is the fifth input and the fifteenth output of the command switch and the first input of the Write-Read mode switch, the second input of the third element And connected to the exit m of the third element is NOT, the output of the third element AND is with the counting input of the counter and is the third output of the Write-Read mode switch, the output of the fourth element is the fourth output of the command switch and the fifth input of the address switch, the output of the first element is NOT the fifth output of the command switch and the fourth input of the Write-Read mode switch, the input of the second element is NOT the sixth output of the address switch and the tenth input of the command switch, the output of the second element is NOT I have the sixth output of the command switch and the fifteenth input of the address switch, the inputs of the fourth and fifth elements are NOT connected to the common bus, the output of the fourth element is NOT connected to the second input of the counter and is the ninth output of the command switch and the twelfth input of the Write-Read switch, the fifth output the element is NOT the tenth output of the command switch and the sixteenth input of the Write-Read switch, the second input of the counter is the sixteenth input of the command switch and the twelfth the input of the Record-Read mode switch, the counter reset input is the seventeenth input of the command switch and the second output of the Record-read mode switch, the outputs of the counter are connected to the inputs of the decoder, respectively, the first output of the decoder is the fourteenth output of the command switch, the third input of the address switch and the seventh input of the mode switch, "Write-read", the second output of the decoder is the fifteenth output of the command switch, the first, fifth and ninth inputs of the switch pa modes "recording-reading", the third output of the decoder is the sixteenth output command switch and the tenth switch input modes "recording-reading".  3. The switch according to claim 1, characterized in that the address switch contains an M-bit counter, an M-bit decoder, two AND elements, the first input of the first AND element connected to the output of the second AND element and the counter reset input, the second input of the first element And connected to the first output of the M-bit decoder and is the second input of the address switch, the output of the first element And is the first output of the address switch and the thirteenth and fifteenth inputs of the Write-Read mode switch, the first input of the second element And I is the third input of the address switch, the fourteenth input of the command switch and the seventh input of the Write-Read switch, the second input of the second element And is the fourth input of the address switch, the output of the fourth communication line of the input-output bus, the first, fourth and ninth inputs of the command switch, the counter input of the M-bit counter is the fifth input of the address switch and the fourth output of the command switch, the second input of the M-bit counter is the sixth input of the address switch the torus and the sixth output of the Write-Read mode switch, the outputs of the M-bit counter are connected to the inputs of the M-bit decoder, the outputs of the decoder are the corresponding inputs of the key block.  4. The switch according to claim 1, characterized in that the Record-Read mode switch contains two RS-flip-flops, four AND elements and two OR elements, the R-inputs of RS-flip-flops are the first outputs of the address switch, the S-input of the first The RS-trigger is connected to the second input of the third AND element and to the output of the first AND element, the first input of the first AND element is connected to the first inputs of the third AND element and the first OR element and is the fifteenth output and fifth input of the command switch, the second input of the first AND element is the first output m of the command switch, the first input of the second element AND is connected to the output of the first element OR, the second input of the second element And is the fifth output of the command switch, the output of the second element And is the seventeenth input of the command switch, the output of the third element And is connected to the output of the fourth element And is the fifteenth the input of the command switch, the first input of the fourth element And is the fourteenth output of the command switch, the second input of the fourth element And is connected to the output of the second RS-trigger and I is the (8k + 2) -th input of the key block, where k = 0,1, ..., M, M is the number of channels, the second input of the first OR element is the sixteenth output of the command switch, the first input of the second OR element is connected to the common bus , the second input of the second OR element is the ninth output of the command switch, the output of the second OR element is the sixth input of the address switch, the output of the first RS-trigger is the (8k + 2) -th input of the key block, where k = 0,1, ..., M, M - the number of channels, the output of the second RS-trigger is connected to the second input of the fourth element And and is is the (4M + 4k + 2) -th input of the key block, where k = 0,1, ..., M, M is the number of channels.

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