SU1259335A1 - Non-volatile storage - Google Patents

Abstract

The invention relates to computing technology and can be used in permanent memory devices on integrated circuits. The aim of the invention is to increase the reliability of the device. The device contains a logic analysis block, an address register, an address decoder, a memory block and a synchronization block. The logical analysis block contains two comparators for each bit of the memory block, analyzing the logic zero levels and output signal units, the ORDER elements and the OR element, and the word memory block regeneration signal when the logic level degradation is detected. The device provides The control of all cells of the memory block word is read during each cycle of reading the information. 1 hp f-ly, 3 ill. (L of the joint venture "its od sp

Description

The invention relates to computing.

The aim of the invention is to increase the reliability of the device.

FIG. 1 is a diagram of a memory device with information protection from destruction J in FIG. 2 is a diagram of a synchronization unit; FIG. 3 is a diagram of a control unit.

The acquisition unit (Fig. 1) contains a logical analysis unit 1, an address register 2, a decoder 3 a memory block 4, a synchronization block 5. FIG. 1 also shows the external control unit 6, the inputs and outputs 7-21 of the synchronization unit.

The synchronization unit (Fig. 2) contains inverters 22 and 23, element AND 24, RS-flip-flop 25j D-flip-flops 26-2 element AND-NOT 29, elements And 30 and 31, inverter 32, element And 33, D-flip-flop 34 , the element OR NOT 35 and the element 36 delay,

The unit of logical analysis (Fig. 3) contains the element OR 37, comparators 38 and 39 and the elements CLEAR OR 40

The storage device works {as follows.

The control unit 6 impulses the address tracking pulse (ISA) and exposes the address to the address information bus (Fig. 1). Next, an external device request signal is set (3 pr) and a read signal (3 p / ch) and with the arrival of the clock signal, the address is written by a signal from the pair element 24 (fig. 2) to address register 2 (fig. 1). If the recorded address matches the zone of the memory block 4, the address decoder 3 issues a signal to the NAND 29 element which sets the trigger 25 to one state (Fig. 2). The trigger 25 provides a selection signal to the third control input of the memory unit 4. Since the control unit 6 sets the reading mode, the second element 30 triggers and gives the enabling signal to the informational 1st input of the trigger 26, which is triggered by the arrival of a clock pulse and the forg-ers read signal to the inverse output that goes to the fourth control input of the unit . 4 memory, while from the direct output of the trigger 26, an answer signal is given to the seventh input 21 of the control unit 6 via the element OR-NOT 35. Thus, for memory block 4, all

the necessary signals for reading the information, i.e., the address register 2 sets the address where it is necessary. to read the information, the trigger 25 selects the crystal memory, and the trigger 26 sets the mode of its operation and reading. I} Eformation from the inputs-codes of the memory block 4 via the address information bus enters the Lenin control unit 6 for processing. The trigger 26 gives an external device response signal through the OR-NOT element 35 from the seventh output 19 of the synchronization unit 5 to the input of the control unit 6, as soon as

5 information will be read in block 6

control, it removes the request signal and the information comes from the first output 7 of the synchronization unit to the first input of the register 2 address, resets the register 2 and the triggers 25 and 26.

 reading is over. In the read cycle, the information read out from memory block 4 is fed to the inputs of comparators 38 and 39 (Fig. 3) for analysis.

S If the cell of memory block 4 (n-word) contains at least one logical unit, then it is subjected to an analysis of the level of degradation. The comparator 38 (Fig. 3) is triggered in

0 if the level of the detected signal is greater than the maximum permissible level of logical zero, i.e. It is always generated when a logical unit is read. Comparator

55 39 does not work when a unit is crossed if its level is lower than the allowable one. In this, at the output of the EXCLUSIVE OR 40 element a logical unit appears,

0 which gives permission to operate the trigger 34 (FIG. 2) through the OR element 37 (FIG. 3), the trigger 34 is triggered if there is a resolution at the end of the reading cycle and its inverse

The 5 rdscode signals the control unit 6 to regenerate the read information at this address. By. this signal, the control unit sets again the same address as

0 in the previous cycle, generates PICA, DPR signals and records for which the clock signal again records the address; the address is in the 2 address register, triggers trigger 25 (Fig. 2), resolves the trigger bot 27 together with the Record signal, the signals from the element And 33 and with the trigger 34 (through the element And 33) allow the operation of the trigger 28.

With the arrival of the clock signal, the triggers 27 and 28 are triggered and send the Record and Erase signals from the fifth and sixth outputs 17 and 8 of the synchronization unit 5 to the fifth and sixth inputs of the memory 4, respectively (Fig. 1 and 2). Thus, in block 4, the memory erases the information in the cell in which the information is to be regenerated (register 2 addresses set the address where the information should be erased, trigger 27 selected block 4 of memory, and triggers 27 and 28 formed the Record and Erasing). At the same time, the trigger 27 allows the delay element 36 to operate (Fig. 2), which after a strictly defined time (2-5 ms) outputs the Response signal from the seventh output 19 of the control unit 6 through the OR-NOT 35 element to the input of the control unit 6 Trigger 28 resets trigger 34 when set to one. The delay element 36 is needed to set the write and erase cycles in memory block 4 more than the read cycle. With the arrival of the signal, the response from the output 19 of the synchronization unit 5 to the input of the control unit 6 from the element OR NOT 35, unit 1 removes the request signal, which, arriving at the third input 11 of the synchronization unit 5, resets the triggers 27 and 28. The erase cycle is over . Then, the control unit 6 similarly repeats the cycle of writing to the same cell, only on the address information bus is set by the information control unit 6 to be recorded, and the trigger 28, which generates the Erase signal, does not work, because the trigger 34 The information read from this cell is recorded again, i.e. the regeneration process takes place. The described process occurs every time if the comparators 38 and 39 (Fig. 3) fix the degradation of the signal level below the permissible value. If it is necessary to write new information into any memory cell, then the control unit 6 generates an erase signal, which sets the trigger 34 in one unit.

0 5 0 5 about 0

five

0

five

condition. The trigger sets the Regeneration signal to the eighth output 20 of the synchronization unit 5, which is fed to the input of the control unit 6. Subsequently, the process completely coincides with the cycle of regeeration, only control unit 6 replaces new information for writing to the memory cell.

Claims (2)

1. A storage device with information protection from destruction, containing the address register, whose outputs are connected to the addresses of the address decoder, and the control inputs are connected to the outputs of the first group of the synchronization unit, and a memory unit, characterized in that reliability, a logic analysis block is entered into it, where the inputs of the logic analysis block are connected to the outputs of the memory block, the information inputs of the address register and are the information-information inputs-outputs of the device, the address inputs of the memory block connected to the outputs of the address register, and the control inputs are connected to the outputs of the second group of the synchronization unit, the outputs of the third group and the inputs of which are respectively the control outputs and device inputs, and the first and second inputs are connected respectively to the output of the address decoder and the output of the block logical analysis. 2. The device of claim 1, wherein the logical analysis unit contains comparators, the EXCLUSIVE OR elements and the OR element, and one of the inputs of the comparators are pairwise combined and are the inputs of the logical analysis block, and the other. These inputs are connected to the buses of the corresponding reference voltages, the outputs of the Comparators of each pair are connected to the inputs of the corresponding EXCLUSIVE OR elements, the outputs of which are connected to the inputs of the OR element whose output is the output of the logic analysis block. . and.  op1 38 w 37 Uonz I 39 Ix " Editor A.Vorovich Compiled by O. Isaev Tehred M. Khodanich Proofreader I. Muska Order 5128/50 Circulation 543 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Fig.Z