SU1187174A1 - Multilevel device for switching processors in multiprocessor computer system - Google Patents

Abstract

1. MULTILEVEL DEVICE FOR COMMUNICATION OF PROCESSORS IN MULTIPROCESSOR COMPUTING SYSTEM, containing switching modules at each level, and switching modules of each lower level group are connected via buses to corresponding higher level switching modules, each low level module is connected by communication buses processors, each module is switchable. It contains a control unit, a main storage unit, a storage unit of memory, a channel index storage unit, a block of buffer registers, the first input of which is the input / output of the communication bus of the switching module, the control output of the control unit through the control bus is connected to the control input memory block, memory block, channel index memory block, buffer register block, characterized in that, in order to improve performance due to simultaneous and independent establishment of logical channels , the free indices register of channels, the first and second priority encoders, the decoder is set1 and the reset decoder, the indicator register block, the write decoder, the multiplexer block, the direction decoder, the block of OR elements, the information input / output of the control block are connected to each switching module, the data decoder to the information input-output of the RAM block, the memory block of channel indexes, to the second input-output of the block of buffer registers, to the information input of the block of indicator registers, cheap installation unit, to the first input of the OR block, to the outputs of the multiplexer block and the memory block, whose address input is combined with the second input of the OR block and connected to the output of the first priority encoder, the output of the OR block of the element, to the reset decoder information input, the outputs of the installation descrambler and the reset decoder 00 are connected to the installation inputs and the free index register of the channels whose output is connected to the input of the first priority encoder 4, the output of the block address y control is connected via the address bus to the address input of the direction decoder, recording decoder, channel index memory, multiplexer block, the control output of the control unit is connected via the control bus to the gate input of the set decoder, reset decoder, write decoder, direction decoder, blocking input of the multiplexer block, write decoder, direction decoder, blocking input of the multiplexer , the output of the direction decoder is connected to the input of the selection of the block of buffer registers, the output of which is connected

Description

It is connected to the input of the second priority encoder, the output of which is connected to the input of the control unit.

2. The device according to claim 1, of which is that the control unit comprises a clock generator, an arithmetic logic node, a control memory node, an input data memory node, an output memory memory, a multiplexer firmware address, data multiplexer, address register, firmware address register, microcommand register, base address register, result register, control decoder, selector decoder for the NOT element, and the output of the clock generator is connected to the microcircuit IDA, the result register, the address register, the base address register register and the microprogram address register, the formative input of which is connected to the multiplexer output of the microprogram address, and the output to the input node of the control memory, the first output of which is connected to the information input of the microcommand register, and the second output is with the first and second inputs of the multiplexer of the firmware address, the control input of which is connected to the first output of the register of the microcontrol, the second output of which is connected to the address input of the multiplex ra data, third

the output is with the operation code input of the arithmetic logic node, the fourth output is with the control decoder input, the fifth output is with the control output of the block, and the sixth output is with the enable input of the memory node of the input data and through the element NOT with the input resolution of the memory node This output, the output of which is connected to the input of the input data storage node and the information input-output of the block, the output of the input data storage node is connected to the first information input of the data multiplexer, the second information input of which is the input of the block, and the output is connected to the input of the first operand of the arithmetic logic unit, the output of which is connected to the information inputs of the result register, the address register, the output of the result indicator — to the first input of the multiplexer of the firmware address, and the second operand to the output of the result register the output data memory, the first, second, and third outputs of the control decoder are connected to the gates of the output of the result register, the address register and the base address register, respectively, respectively register address is the address output unit, an output register connected to the base address input selection decoder, the output of which is the output of the control unit.

one

This invention relates to automation. and computing and can be used in the construction of high-performance and highly reliable computing and information systems.

The purpose of the invention is to increase productivity by increasing connectivity in the interconnect structure of switching modules and enabling simultaneous interaction between different computational modules along different paths through switching modules.

Figure 1 shows the structural scheme of a multiprocessor computing system; figure 2 - structural diagram

switching module; FIG. 3 shows an example of the implementation of the block diagram of the control unit; figure 4 is an example of the implementation of one buffer register block buffer registers; FIG. 3 is an example of implementation of a computing module; 6 and 7 are flowcharts for the input and output mode, respectively. 10 The computing system (FIG. 1) contains computing modules 1, switching modules 2. Each switching module 2 (FIG. 2) contains a control block 3, a main memory block 4, a channel 5 free index register, a first priority encoder 6, a second priority encoder 7, a set decoder 8, a decoder 9 reset, a read memory block 10, channel index memory unit 11, indicator register register unit 12, write decoder 13, multiplexer unit 14, buffer register unit 15, direction decoder 16, group of elements OR 17, data bus 18, address bus 19, control bus 20, bus 21 st zi The control unit 3 (FIG. 3) contains the microprogram address register 22, the control memory node 23, the micro-command register 24, the microprogram address multiplexer 25, the arithmetic unit 26, the control decoder 27, the result register 28, the address register 29, the base address register 30 , a selection decoder 31, an output data memory node 32, an input data memory node 33, data multiplex 34, a NOT element. 35, generator of 36 clock pulses. Each register from the buffer register block 15 (FIG. 4) contains output data register 37, output memory node 38, output trigger 39, first element NOT 40, first element 41, output data register 42, input memory node 43, trigger 44 reception, the second element is NOT 45, the second element is AND 46, the trigger 47 of the mode, the third element is AND 48, the fourth element is AND 49, the element OR 50, the control information storage node 51, the status memory node 52, the output 53 of the read signal, write signal output 54, reset signal output 55, status reading signal output 56, informational bidirectional Inu 57, the output 58 of the signal tracking, the input acknowledgment signal 59, input 60 accompaniment signal output handshake signal 61, the output 62 timing mode, input 63 Sygra synchronization mode. Computing module 1 contains input information register 64, output information register 65, microprogram memory 66, microprogram multiplexer 67, microprogram register 68, register 69, battery, multiplexer 70, battery, memory address register 71, random memory 72 , arithmetic logic 55 block 73, input tracking 74, output acknowledgment input 75, input mode input 76, output rotate for 77 output 77, input acknowledgment output 78, output mode output 79, information bus 80, Table 1 shows the logical 1-4 st Oka and arithmetic 5 - 8 lines operations performed by the arithmetic-logical unit 26 and block 73, where A - the first operand; B is the second operand, W is the input of the operation code, S is the output of the result, P is the output of the indication of the result, © is the logical operation EXCLUSIVE IL, L is the logical operation AND, + is the arithmetic addition, X is the value not defined, O and 1 - binary values of signals, - - inverse signal value. LLL .. String The following algorithm is used for the operation of the computational module 1 with the switching module 2 of dp transmission of information on communication buses 21. In the event of a shortage of own resources, the computational module 1 from the computation mode enters the exchange mode and forms a packet using the microprogram in the memory 66 of the microprograms and the arithmetic logic unit 73, and through the register 69 the battery records it into the RAM 72, Computational module 1 source using the firmware sets the signal at the output 79 of the mode to the output. It is processed by switching modules that establish communication buses with the computing module 1 receiver and is transmitted to the mode input 76 to the input of the computing module 1 receiver, which, under the control of the microprogram, processes it and outputs a signal at the output 78 of the handshake for input appointment. Having passed through the switching modules, it is fed to the input 75 of the receipt for the output and, having passed through the mule typelexer 67 of the firmware, is written to the register 68 of the firmware. The signal from the first output of the register 68 reads the first word from the transmitted packet and transfers it through the multiplexer 70 battery, arithmetic logic unit 73, regis 69 battery to the output register 65. Further, under the action of the firmware, the read word from the register 65 is transmitted to the information bus 80, in addition, a tracking signal is output on the tracking output 77 to the output. Passing through the switching modules, the transmitted word via the bus 80 of the information module of the receiver module is recorded in the input information register 64, and the tracking signal through the tracking input 74 is input-to-firmware multiplexer 67; and from it to the register 68 firmware. Under the control of the firmware, the received word is written into the operational memory 72 and a receipt is received for receiving the word from the output 78 of the acknowledgment to the input, which is transmitted through the Switching modules to the computational source module via the input 75 of the acknowledgment to the output in the multiplexer 67 of the firmware. Upon receipt of the receipt of the word, the source computer module uses the described algorithm to transmit the second word, etc. Upon receiving the receipt of the last transmitted word from the packet, the source computer module removes the signal from mode output 79 to output and goes into the calculation mode, and the receiver module proceeds to process the received packet and perform the necessary calculations. After the completion of the calculations, the results are transmitted to the computational module of the source according to the described algorithm. Switching modules 2 (Fig. 6) that are not currently occupied by servicing computing modules 1 are in the input waiting mode, while they interrogate the code of input requests from other modules arriving at input 63 of the mode synchronization signal per trigger 47 modes. At element 49, an analysis is carried out for the presence of input requests, and if they are not present, the polling mode continues, and if they exist, one priority request is allocated on the priority encoder 7 and the switching module 2 switches to input mode. From the element 46, an acknowledgment signal is issued to the priority request on the output 61 of the acknowledgment signal, and the module 2 waits for a tracking signal on the input 60 of the tracking signal, which is fixed on the receive trigger 44. Thereafter, input is delayed at the output memory node 38, a data byte is received on the bidirectional bus 57 to the input data register 42, and the input request is analyzed on the And element 49. If the request is not cleared, then the tracking signal and the next data byte is received, and if the request is cleared, then the switching module 2 removes the acknowledgment signal at AND 46 and switches from input mode to output mode. Switching module 2 (FIG. 7), having received the data block, sets the code for output requests in mode trigger 47 at mode synchronization output 62, receives the code of input responses through input 59 of the acknowledgment signal to issue trigger 39 and analyzes the presence of responses on terminal 48: if there are none, then it waits to receive responses, and if they do, it fixes the priority code of the output requests for the responding computing modules 1 on the priority encoder 7. After that, the data byte on the data bus 18 is loaded into the output register 37 and output from drove tracking from element 41 on output 58 of tracking signal; output node 38 delays output memory and analyzes data block end on control information memory node 51: if not the end, then loading the next data byte, and if the data block end , then clearing the code of the output requests on the mode trigger 47, and the switching module 2 goes into the input waiting mode. The proposed multiprocessing computing system works as follows. 7 Each computational module 1 included in the system can be located in free or active mode. All computational modules are bits per types, and there can be any set of modules 1 having the same type in the system. Free computing modules 1 do not perform calculations. They transition to the active (busy) state according to commands coming from other active computing modules 1 that have performed the calculations. In this case, a logical communication channel is established between the active newly activated computing modules through the switching modules 2, through which information can be exchanged between them later on. The formation of a logical channel to a free computing module is carried out in cases where some active computing module needs, for example, an additional amount of RAM or an additional calculator to parallelize the computing process. The search for a free computing module of a certain type and the simultaneous establishment of a logical channel to it is carried out by each switching module 2 decentralized on the basis of service information stored in block 12 indicator registers in each of modules 2. Each m-th (t 1, n) of n The registers of block 12 stores indicators that indicate with what types of computing modules you can establish a logical communication channel, if you search in the th direction, i.e. through the th buffer register of the block 15, connected to the m bus of communication 21 of the given switching module 2, in each register of the block 12 for storing one indicator corresponding to one type of computing modules, one bit is used. Therefore, when searching for freedoms module of a certain type in module 2 is analyzed. with the corresponding indicators in each of the registers of block 12. When the first unit indicator is in the m-th register, the 12 th-th direction is selected in this module 2 by establishing a logical communication channel, and the search command is issued on the -th bus 21 to the next switching module 2 or to the required computing module 1. Establishing a logical channel through some module 2 consists in allocating in that module 2 a separate free channel index to implement the logical communication channel to be established. The free channel index is allocated from the .5 free channel index register. Its binary code is read through memory reading unit 10 onto data bus 18 and can be stored in one of the channel index storage units 11. At the same time, the newly occupied index is reset in register 5 with the help of the reset decoder 9. The j number of block 11 is determined by the number of the direction from which the computation module search command was received (J 1, p). The cell address in block 11 is determined by the channel index, which was allocated by the previous switching module 2 and issued with the search command to this module 2. The same register cell 11 can contain the number m of the register of block 12, in which the indicator is found, which allows in the future, to transmit information through the logical channel that goes out in this module 2 along the m-th line and goes into the je direction. If it is necessary to create a two-way logical channel, the mirror procedure for recording the received channel index is carried out in the m block 11 at the address determined by the newly occupied channel index. After a search command is received in a free computing module, it enters the active state and issues a command to reset its type indicator. By this command, each switching module 2 resets this indicator to the register of block 12 by writing a zero to the corresponding bit. The required register of block 12 is decoded by the write decoder 13 when it decoding the number of the input direction from which the command was received. This command is issued to all other directions, if in all registers of block 12 this indicator is also reset. Thus, the newly occupied computing module is excluded from the number of free ones and not a single search command will enter it. After the release of the computer 9118717410

When the module is completed in other registers of block 12, this task, it issues the installation command; the indicator has not been set. Blade Indicator. When this is received in a multilevel structure command in some module 2 commutator round of modules 2 again, it sets the indication; 5po is the service information; To the torus in the corresponding register, the logic 12 is allowed to establish with it. When installing the indicator, the communication channel is calculated in other directions when the search module is of this type.

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Claims (2)

1. MULTI-LEVEL DEVICE FOR COMMUTATION OF PROCESSORS IN A MULTI-PROCESS COMPUTER SYSTEM, containing at each level switching modules, the switching modules of each group of a lower level are connected via communication buses to the corresponding switching modules of a higher level, each lower level module is connected by communication buses to processors, each commutator module. The unit contains a control unit, a RAM unit, a read memory unit, a channel index memory unit, a buffer register unit, the first input of which is the input / output of the communication module communication bus, the control unit control output via the control bus is connected to ^{: the} control input of the read memory unit, RAM block, channel index memory block, buffer register block, characterized in that, in order to increase productivity due to the simultaneous and independent establishment of logical communication channels, each the first switching module, the register of free channel indices, the first and second priority encoders, the installation decoder, the reset decoder, the indicator register block, the recording decoder, the multiplexer unit, the direction decoder, the unit block OR, the information input-output of the control unit are connected via the data bus to the information input - the output of the RAM block, the channel index memory block, to the second input-output of the buffer register block, to the information input of the indicator register block, the decoder is set In addition, to the first input of the block of OR elements, to the outputs of the block of multiplexers and the read memory block, the address input of which is combined with the second input of the block of OR elements and connected to the output of the first priority encoder, the output of the block of OR elements is connected to the information input of the reset decoder, the outputs of the setup decoder and the reset decoder are connected to the installation and reset inputs of the register of free channel indices, the output of which is connected to the input of the first priority encoder, the output of the control unit address is connected via at the address of the address input of the direction decoder, recording decoder, channel index memory block, multiplexer unit, the control unit control output is connected via the control bus to the gating input of the unit decoder, reset decoder, recording decoder, direction decoder, blocking input of the multiplexer block, direction decoder output connected to the input of the selection block buffer registers, the output of which is connected to the input of the second priority encoder, the output of which is connected to the input of the block is controlled i. 2. The device according to π.1, with the fact that the control unit contains a clock generator, an arithmetic logic unit, a control memory unit, an input data memory node, an output data memory node, a firmware address multiplexer, a data multiplexer, address register, firmware address register, microcommand register, base address register, result register, control decoder, selection decoder and element NOT, and the output of the clock generator is connected to the synchronization inputs of the register 'microcommand , a result register, an address register, a base address register and a firmware address register, the information input of which is connected to the output of the multiplexer of the firmware address, and the output is to the input of the control memory node, the first output of which is connected to the information input of the micro command register, and the second output - the first and second inputs of the multiplexer firmware address, the control input of which is connected to the first output of the microcommand register, the second output of which is connected to the address input of the multiplexer s, the third output is with the input of the operation code of the arithmetic-logical unit, the fourth output is with the input of the control decoder, the fifth output is with the control output of the unit, and the sixth output is with the input of the resolution of the input data memory node and through the element NOT with the resolution input of the memory node output data, the output of which is connected to the input of the input data memory node and the information input-output of the unit, the output of the input data memory node is connected to the first information input of the data multiplexer, the second information input of which is the input block, and the output is connected to the input of the first operand of the arithmetic-logic device, the output of which is connected to the information inputs of the result register, address register, the output of the result indicator to the first input of the microprogramm address multiplexer, and the input of the second operand to the output of the result register and to to the input of the output data memory node, the first, second. and third outputs of the control decoder are tuned to the gates of the output of the result register, address register and base address register, respectively, the output of the address register is the address output of the block, the output of the base address register is connected to the input of the selection decoder, the output of which is the control output of the block.