SU1239724A2 - Device for exchanging data - Google Patents

Abstract

The invention relates to the field of copying technology and can be used in computing systems: max for interfacing computers with communication channels. The aim of the invention is to expand the class of tasks to reduce the time spent by a computer to conduct an exchange with lower-level devices. The goal is achieved by the fact that a device containing a pulse clock generator, a firmware control unit, an interrupt unit, a linear I / O unit, linear terminators, a linear controller. a key decoder, a register block, an I / O decoder, a memory block, a control decoder, a second clock generator and a microprocessor control block, a gateway block, a line capture resolution block, a second and third memory blocks, and a group of memory blocks . 2 hp f-ly, 1 ill. (3 S (L to 00 with 1C 4 N)

Description

The invention relates to computer technology, can be used in computer systems for interfacing computers with communication channels, and is an improvement to the known HOFO device by author. St. No. 1012235, The purpose of the invention is the expansion of the class of tasks to be reduced to reduce the time spent by the computer on exchanging with devices of the lower level:

Figure 1 presents the block diagram of the device; Figures 2 to 7 illustrate functional diagrams of a communication unit with a trunk, an interrupt unit, a firmware control unit, a linear I / O unit, an interface unit, and an access authorization unit.

The device (Fig. 1) contains generators 1 and 2 clock pulses, blocks 3 and 4 of microprogram control having clock 5 and 6, respectively, synchronizing 7 and 8 inputs, first and second highways, including respectively addresses, data and control 9-14 , interrupt unit 15, having first 16 and second 17 inputs, group of inputs 18, first 19 and second 20 outputs, communication unit 21 with a highway, first inputs 22 and output 23 of which are a sampling input and a synchronization output, a. the second input 24 and output 25 and the group of address inputs 26 and information input-outputs 27 are intended for communication with the second highway, the linear input-output unit 28, the second input-output of which is connected in series with the highway 29 of communication unit 30 with lines for serial I / O to linear connectors 31, the second inputs-outputs 32 of which are linear inputs-outputs of the device, linear decoder 33, block 34 of registers, decoder 35 I / O, first block 36-RAM, control decoder 37 , block .38 conjugation, block 39 times decisions — access to the trunk, bus 40–43 second and first inputs and outputs, block 39, second 44 and third 45 blocks, memory, group of blocks 46 of the driveway.

Block 21 connection with the highway,. (FIG. 2). contains memory 47, second and first address registers 48 and 49, second and first 50 and 51 data registers, second and first elements AND 52 and 53, OR element 54, triggers 55 and

five

0

five

0

five

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five

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56, the second and first delay elements 57 and 58, the address comparator 59, the pulse generator 60 and the HE element 61.

Interrupt block 15 (FIG. 3) contains a comparator 62, elements And 63 and 64, triggers 65 and 66.

Blocks 3 and 4 of the firmware control (Fig. 4) contain a buffer register (buffer) 67 of data, -. arithmetic logic unit (ALU) 68, instruction register 69, general registers block 70, clock pulse generator 71, instruction decoder 72, command counter 73, address register 74, output register 75, input register 76, buffer register (buffer ) 77 addresses.

The linear input / output unit 28 (FIG. 5) contains a buffer register (buffer), 78 data, and a 79 register. mandr and modes, shift register 80 for transmitting information, state register 81, shift register 82 for receiving information, decoder 83.

Interface unit 38 (Fig. 6) contains groups 84 and 85 of tristable AND elements, AND elements 86-92, OR elements 93, and delay element 94.

The highway access permission block 39 (FIG. 7) contains AND elements 95 and 96 and HE elements 97 and 98.

I

Block 21 of 1zi with backbone is a random-access memory device for storing and accumulating transceiver arrays and for informational communication with block 4 of microprogram control over the second trunk and has access channels as from the second trunk side, and from the first highway. The time distribution of the access cycles to block 21 is performed by triggers 55 and 56, the unit state of which determines the passage of the address, data and control signals to the input of memory 47. The triggers 55 and 56 are connected in such a way that their simultaneous single state is excluded . If the state of the flip-flop 55 corresponds to one, then the signal from the output of this flip-flop arriving at the setup input of the flip-flop 56 keeps it in the zero state and vice versa. On-time distribution

The flip-flops are carried out by mutually inverted signals from generator 60, using the element HE 61, to their clock inputs. Signals indicating the start of the reference cycle arrive at the information inputs of the triggers. A return signal from the second trunk is generated at the output of the comparator 59, depending on the state of the inputs 26 connected to the address bus. The presence of the comparator 59 is determined by the different address capacity of the address bus and the memory 47. For example, sixteen bits of the address bus (inputs 26) are needed to organize the addressing to memory blocks 45 and 46, and the memory capacity 147 is 1 kilosword, for addressing to which only ten tirasr of the bottom address bus is needed. 0c tavates six address bits are like the part number of the whole possible in the array, and they are compared with a predetermined number in the address comparator 59. When a given number matches a number corresponding to the address bus status, a sampling signal is generated at the output of comparator 59. If the state of the flip-flop 56 coincides with the zero state, then the flip-flop 55 is set to the one state at the clock edge. The signal from the output of this trigger, arriving at the inputs of the register 50 data

And 52, the register .48 of the add and the delay element 57, allows the passage of address signals, data control to the memory inputs 47 and signal generation. Response to block 4. The input 24 signal from the second highway control bus 14 determines the direction of data movement through register 50 (for writing or reading).

If the state of flip-flop 56 corresponds to a single state, then the installation of flip-flop 55 is delayed until the flip-flop 56 is set to zero, the delay is the same response at output 25 for block 4 and the passing of address, control and data signals. - -,

A sign of access to block 21 from the first line is a sampling signal at input 22. Operation. block 21 in the subsequent cycle is similar except that registers 49 and 51, delay element 58 and AND element 33 are involved in this cycle.

ten

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,,

- 55

2397244

Output 18 of block 21 is intended to signal the address of a selectable cell from memory 47.

Interrupt unit 15 is designed to generate interrupt signals to block 4 through output 20, and to block 3, via output 19. Interrupt signals are generated using the address code of block 21 and depending on the access mode (read, write).

Out of the total NfaccHBa of the memory 47 of the block 21, three addresses (three cells), X, Y, and Z, which perform the function (5 state (Y), command (y), and linear matching ad (z) are allocated. , corresponding to the display of one of the cells, is performed by the comparator 62 by comparing the code of the current address of the address with the predetermined codes. The codes of the current address of the address are fed to inputs 18 from the output of block 21.

If cell X is accessed, a comparator 62 connected to AND 64 and trigger 50 is given a signal, and depending on the presence of a signal at inputs 17 or 16, the trigger 66 is set to either one or zero. Therefore, if a cell is being accessed. X from the side of the second highway, the trigger 66 is set to a single state (an interrupt signal is generated in the direction of the program control unit 3), if the cell X is accessed from the first highway, the trigger

 66 is set to the zero state (the interrupt signal is reset to the side of block 3).

When accessing the cell Y, the control of the trigger 65 (interrupt signals 45 nor to the side of the second highway) is carried out in a similar way, only with

using element I 63. I

Blocks 3 and 4 are designed to implement the programs stored in memory blocks 36 and 44, respectively, as a result of which the operation of the device blocks is coordinated. Blocks 3 and 4 execute a specific list of commands, including read-write commands,. logical and arithmetic data processing, conditional and unconditional branches.

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Arithmetic logic unit 68 ensures the processing of binary-coded data.

General registers block 70 is designed to store and store data involved in the processing and execution of a given command, and command register 69 to receive the command and store it during the execution of a command.

The decoder 72 commands, decrypting, em command code and extracts myco-operation control in accordance with the received command.

The command counter 73 is designed to receive, form and store the current address of the command, and the address register 74 is designed to receive and store the address and issue it to the address buffer 77 during the cycle to access external blocks. The shaper 71 clock pulses is designed to generate clock pulses that synchronize the operation of the block.

Data buffer 67 is bi-directional tristable circuits designed to determine the direction of data movement when communicating with external blocks.

Output signal register 75 is used to generate control signals (write-read), and input signal register 76 is used to capture input control signals that ensure operation of the block with external blocks.

Block operation cycle: always starts from reading the command to the address generated in the command counter 73, which is decoded by the decoder

72 commands, at the output of which control signals are generated that determine the sequence of passing. no address and information signals. For example, when executing read-write commands, the address of the external block from the control word enters the address buffer 77, a read-write control signal is generated, and the direction of data flow is determined through the data buffer 67. Then, depending on the state of the input signals detected by the input signal register 76, the block enters the mode of waiting for the end of the exchange cycle. After the exchange is completed, the next command address is generated. Teams condition-5

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or unconditional branches, control the state of the command counter 73 on the basis of information obtained earlier or in the current command.

Linear input / output unit 28 is intended for 51 receiving and transmitting serial data. Conversion of serial code into parallel data code and vice versa pro-. is in shift registers 82 and 80, respectively. Synchronization of the conversion end is performed via the state register 81, the corresponding bit of which determines whether the linear block 28 is ready either to receive or to transmit the next data word.

Register 79 of commands and modes is designed to determine the start of reception or transmission during the operation of the device. The sampling signals of one of the registers are generated by the decoder 83 based on the information received via the address bus 9 and in the presence of a control signal on the control bus 11.

The direction of data flow on bus 10 through buffer 78 is determined by control signals on bus 11 when there is a sampling signal on bus 9. The buses for transmitting serial data and conversion synchronization signals form the receive-transmit line 29.

The register block 34 is intended ,,. for storing the number of one of. linear adapters arriving at the linear decoder 33, at the output of which a sampling signal of the corresponding linear matcher 31 is formed.

Depending on the field of application of the proposed device, the linear coordinators 31 (the number of which depends on the required number of communication channels of the device) can be either an electronic key operating on a telegraph channel or a standard demodulator modulator

when working on the telephone channel. I

The control descrambler 37 is started to form sampling signals based on the signals of the bus 9 address of the address to the communication unit 21 with the backbone, to the memory unit 36 and to the linear coordinators 31, as well as to generate a readiness signal to the microprogram control unit 3

upon receipt of a signal from block 21 on output 17.

The I / O decoder 35 forms the signals of the sample either linear

15 14 13 12 11 10 9

Such a distribution of bits of the address signals of the bus 9 makes it possible to evenly distribute the load on the bus circuits of the 9 address.

Block 38 provides the connection of the computer with the second line.

On the control signal of the computer at the output of the element OR 93 and the output 40 of the block, a logical unit is set up, which is a signal of the request for access to the highway (ZDM), If there is a block at the input signal of the permission of access to the highway (RDM), at the output of the element 91 a logical unit is established, which goes to the corresponding inputs of a group of elements And 88, elements And 86, 87 and 92 and element 94 delay. The group of elements And 88 allows the passage of address signals from the input to the output of the block, the elements And 86 and 87 (depending on the control signal LAP or CTN) at their outputs expose a logical unit or zero, according to which groups 84 and 85 of tristable elements And they pass the data from the second group to the first group of input-output data of the block or vice versa, the logical unit from the output of the delay element 94 allows the control signals CAP or CTN to pass, and the Response signal from block 4 through I 92 as a logical unit arrives to the second control input the output of the block.

block 28 or ditch block,

The distribution of addresses. The address to the blocks can be 5 measures, as follows;

76543210

- V - addresses of memory cells 47 and cells of memory block 36; the register number in the linear block 28 and in the block 34 of registers; On - appeal to the linear block 28 input - output, 1 - to the block 34 registers; 00 - access to memory block 36;

10- access to the communication unit 21 with the trunk

11- appeal to linear coordinates 31Г

Block 39 performs the procedures for capturing the second highway either from the computer side or from the block 4 side.

A signal from the EMD from block 38 when there is no signal from the EDM from block 4 at the output of the element I 95 appears a logical unit that blocks the passage of the HHM signal from block 4 and enters the output of the block on the bus 41 as an RDM signal for block 38. By the signal of HHD on block 4, the block works in a similar way, with the only difference that the signal of the RDM for block 4 appears at the output of the AND 96 element.

The device works as follows.

Information transmitted from a computer to a lower level device is recorded. via interface unit 38 and the second line into memory unit 45 with the address of the corresponding linear matching 31 in its cell Z. The program control unit 4 recorded in memory block 44 analyzes the cell Z of unit 45 and if there is an address, the contents of this block are rewritten into block 21 and the transmission command code is entered into the cell C of the same block.

Information from block 21, in accordance with the logic of operation of microprogram control unit 3, is transmitted along the first line to the corresponding device of the lower level, and

The firmware control unit 4 at this time zerms the cell 2 of the memory unit 45 and proceeds to wait for a signal of the completion of the transfer.

After the arrival of the signal O about the completion of the transmission unit 3, the unit 4 is transferred to the formation of a command for polling devices of the lower level, starting with the first. In this case, unit 4 records in cell 7 of unit 21 the address of the first linear distributor 31, and in cell X, the information request code, after which it waits for the reception to complete. After receiving the reception completion signal, block 4 forwards the array of information and-from block 21 to the corresponding memory unit 46 of the corresponding memory unit 46 and proceeds to request information on the next channel.

Regardless of the direction of transmission after its completion, block 15 generates an interrupt signal. Moreover, if an exchange command exhibited block 4, then an interrupt signal appears at output 19 of block 15 and arrives at the control input of block 3, and if an exchange command is issued at block 3, then an interrupt signal appears at the output 20 of the block 15 and is fed to the control input of the block 4.; -, In the process of information exchange between the block 21 and the communication lines, the block 3 operates in accordance with the program stored in the block 36 of the memory. The exchange organization algorithm (protocol type, payload formats, control method, etc. can be different. For example, we give an exchange algorithm when working in half duplex synchronous mode, taking into account that at the other end of the communication channel there is an external device that uses the same protocol Block 3, taken into interrupt signal from block 15, reads from a fixed cell -t of memory 47 containing the communication channel number, writes it to block 34 of registers, thereby selecting the appropriate linear consistency 31. Then reads Cell X ( thus dropping the interrupt signal), analyzes the received command and, in the case of a transfer, writes to the register 69 of the commands and modes of the linear I / O unit 18 a command that sets it up for transmission and starts transmitting the stored data array.

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Before transmitting each data word to the transmitter, the state register 81 of the linear unit 28 is read and its readiness for transmission is analyzed. At the time of transmission in block 3, service information may be formed for each word to perform data control in accordance with the selected control method (e.g.,. The parity bit is formed or the cyclic residual code, etc.) is generated.

After transferring the entire array, unit 3 rearranges the linear unit 28 to receive and, reading the state of the state register 81, organizes the waiting from the external device for sending data confirming the reception by the external device of the transmitted array.

Unit 3, upon receiving the readiness sign of the receiver of the linear unit 28, reads the data transmitted by the external device, writes to the cell 47 of the memory 47 the word signaling the unit 4 about the completion of the transceiver cycle, in which signs of reliability of the exchange are formed.

After that, block 3 again goes into the mode of waiting for the interrupt signal (receiving another command from the second line).

Claims (4)

Formula of gain 1. 5 device for data exchange on a.wt, sv. . № 1012235, about t and h and ya with the fact that, in order to expand the class of tasks, the second microprogram control unit, interface block, access block to the trunk, the second and third blocks are entered into it memory, the blocker block .pampy and the second pulse generator, the output of the clock generator connected to the clock input of the second microprogrammed control unit, the output group of which through the second address busbar c. memory blocks with group a ery output interface unit and with a second. the group of address inputs of the communication unit with the bus, the group of information inputs-outputs of the second microprogram control unit is connected via the second data bus to the group of information inputs-outputs of the second, third and group of memory blocks. with the first group of information inputs / outputs of the interface unit and with the second group of information inputs and outputs of the communication unit with the trunk, the group of control inputs and outputs of the second microprogram control unit is connected to the group of control inputs and outputs of the second and third and groups of memory blocks, with the first input of the access permission block to the ma-., gistrali, the second input and output of the communication unit with the highway, and with the second input of the ka interrupts, the second output of which I connected to the control input of the second firmware control unit, the clock input of which is connected to the first output of the access block for the highway, the output and input of the interface block are connected respectively to the second input and output of the access block for the highway, and information inputs-outputs and a group of address inputs - with the corresponding groups of main inputs-outputs and device inputs. 2. The device according to claim 1, about the tl and - so that the interface block contains two groups of tristable elements AND, six elements AND, a group of elements AND, element OR, and a delay element, with the first inputs of tristable elements first the groups and outputs of the tristable elements of the second group are connected to the second group of information inputs-outputs of the block, the outputs of the tristable elements of the first group are connected to the first inputs of the three-stable elements of the second group and the first group of information 20 five 0 unit inputs and outputs, the second inputs of the tristable elements of the first and second groups are connected respectively to the outputs of the first and second elements AND, the first inputs of which, the first inputs of the third and fourth elements AND, the first and second inputs of the OR element, and the output of the fifth element AND with the second group of control inputs-outputs of the block, the first inputs of elements AND of the group are connected to the second group of address inputs of the block second — the inputs of the first, second elements AND of the elements. And the group, input 15 of the delay element and the first input of the fifth el And are connected to the output of the sixth And element, the output of the delay element is connected to the second inputs of the third and fourth And elements, the outputs of which and the second input of the fifth And element are connected to the first group of control inputs-outputs of the block, the outputs of the And elements of the co-dinena group with the group of address outputs of the block, the first input of the sixth element, AND is connected to the output of the OR element and the output of the block, and the second input - with the input of the block. . . 3. The device according to claim 1, about tl and - the fact that the block access permission to the highway contains two elements And two elements are NOT, the first inputs of the first and second elements And connected respectively with the second and first inputs of the block, the output of the first element I is connected directly to the second output of the block and through the first element NOT to the second input of the second element I, the output of which is connected directly to the first output; the block house and through the second element NOT - with the second input of the first element I. 25 0 / f URIAHS Yu data) I am mine 29 From wuHbi 11 С i nh-b / d with dew (, cppaniopa 35 uprs {8len (addresses F (4y.5 OmSem. t s „FEIii o .iГ) I four : Rec, 1Dr. ,,, 4. JJ ... K bus fid W O- MHD S5 42 ZDLU Editor E. Papp Compiled by V. Vertlib Tehred O. Sopko Proofreader M. Pojo Order 3398/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 96 rdm FIG. 7