SU1305698A1 - Interface for linking electronic computer using equipment - Google Patents

Description

The central control unit clock input and, through a frequency divider, to the clock inputs of the exchange control program with the subscriber, the first inputs of which are connected to the group of control outputs of the central control unit, in the computer sub channel, the third condition input and the fourth block output firmware exchange control with a computer are respectively the output and output of the device for connection to the control output and input of the computer, and the fifth, sixth and seventh inputs are respectively with the synchronization input of the computer and modulo control, with the request input of the memory access node and the central control block addressing unit, the start and request outputs of which are connected respectively to the fourth and fifth inputs of the conditions of the computer exchange program control unit, the sixth condition input connected to the start output the memory access node whose polling input is connected to the polling output of the memory of the central control unit, the polling output of which is connected to the central control unit of which is connected to the polling input of the block of the access control central control of the first subchannel of the subscriber, polling output of the callback block to the central control unit of the i-ro subscriber's subchannel (i T, p - T) is connected to the polling input of the callback block of the central control unit i + 1 of the subscriber's subchannel the call to the central control unit of the subscriber's subchannel 5 is connected to the polling input of the callback block to the central control unit of the subchannel of the computer, the polling and start outputs of which are connected respectively to the first and second start inputs of the central control unit , the output of the operation end of which is connected to the reset inputs of the access blocks to the central control unit of the subchannel of the computer and subscriber subchannels, the first startup codes of the access blocks of the central control block of the subscriber subchannels are connected to the group of start inputs of the central control block, the group of mode inputs of which are connected to the eighth output of the block firmware exchange control with a computer with fourth outputs

microprogram exchange control units with the subscriber, the fifth outputs and the second inputs of the conditions of which are connected to the group of inputs-outputs of signs of the central control unit's order, the address output and command input-output of which are connected respectively via the trunk to the address input and information input-output of the memory block the control input of the trunk switching unit connected to the first output, the second output of which is connected, through the trunk to the inputs of enabling the connection of the address counters to the trunk and the exchange of the subchannels of the computer and subscriber subchannels and the enable enable input to the central control unit trunk, the group of inputs of the OR element is connected to the memory start outputs of the central control unit and the subscriber memory access nodes of the computer subchannel, the reset inputs of which are connected to the end of cycle end the memory block, the memory reset trigger of the memory trigger and the first control input of the main switching unit, the second control input and the synchronization input of which are connected respectively to the output am of the first and second elements AND, the first inputs of which are connected respectively to the inverse and direct outputs of the occupancy trigger PA: mti, and the second inputs - respectively to the outputs of the OR element and the delay element input connected to the output of the first AND element and the trigger installation input memory, the inverse output of which is connected to the first input of the third element I, the second input and output connected respectively to the output of the pulse generator and the polling input of the subscriber’s memory access node of the first subchannel of the subscriber The i-ro subscriber's node of the memory access node of the subscriber is connected to the polling input of the subscriber's memory access node i + 1- sub channel, the polling output of the subscriber's memory access node of the n-th subchannel is connected to the memory input of the subscriber the central control, the outputs of the access mode of the central control unit and the nodes for accessing the subscriber’s subchannel and computer subchannels are connected to the group of information inputs of the bus switching unit

and the memory block mode input, in each subscriber's subscriber, the first and second start outputs and the sign output of the request block of the central control unit and the start and stop outputs of the memory access node are connected to the third, fourth, fifth and sixth condition inputs, respectively the exchange microprogram control unit with the subscriber, whose sixth, seventh and eighth outputs are connected respectively to the inputs of the block of the appeal block to the central control unit and the memory access node and to the clock input of the exchange register, the second and third outputs of which are connected respectively to the information input of the word counter and the first information input of the address counter, the output and the second information input of which are connected via a line respectively to the address input and information output of the memory block, information input and output of which is connected to the input- output of the exchange registers of the subchannels of subscribers, the central control unit contains a memory access node, an address counter, a program readiness register, a busy trigger, two emails And, the element OR and the micro control unit, the first to fourth condition inputs and the condition input group of the microprogram control node are connected respectively to the outputs of the first element AND, the stop output and the first start output of the memory access node, control unit and a group of mode inputs of the central control unit; the first, second and third outputs of the firmware control node are connected respectively to the control input of the program readiness register, counting input ohm address counter, a request for a memory access node request and a group of control outputs of the central control unit, and a clock input and a fourth output, respectively, with a clock input of the central control unit and the first input of the second And element and with the output of the end operation of the central control unit and input reset trigger trigger, a setup input and output connected to the output and the first input of the first element AND, the second input of which is connected to the output of the element OR, the group of inputs which are connected to the first and second the start inputs of the central control unit and the main group of the start inputs, the second input and the output of the second element I are connected respectively to the output of the trigger trigger and the output of the interrogation of the central control unit, the first and second information inputs-outputs of the program readiness register connected respectively to the command input-output of the central control unit and the input-output of the signs behind the central control unit, enabling input — with the enable input of the connection to the central control unit and authorization The input of the address counter, the output of which is the address output of the central control unit, the second start output, mode output, reset input, input and output of the polling of the memory access node, are connected respectively to the memory trigger, memory access output, reset input and an input and output polling of the request to the memory of the central control unit 2, the device according to claim 1, characterized in that the memory access node contains four triggers, five AND elements, two OR elements and a switching element, and first trig input Gera is connected to the output of the first element AND and the start and stop outputs of the node, and the output is connected to the first inputs of the second and third elements AND, the output and the second input of the second element AND are connected respectively to the first input of the first OR element and the start output of the node and the reset input node, the output of the fourth element AND is connected to the installation input of the second trigger and the first input of the second element OR output connected to the reset input of the third trigger, and the second input - to the output of the first OR element and the reset inputs of the first, fourth and volts The first flip-flops, direct and inverse outputs of the second flip-flop are connected respectively to the first inputs of the first and fifth elements And, the second inputs of which are connected to the polling input of the node, the output of the fourth trigger And connected to the second input of the third element And whose output and output of the first trigger form the output of the node access mode, the first and the second inputs of the fourth element And are connected respectively with the output of the fifth element And and the output of the polling of the node and with the output of the third trigger, the installation inputs of the third and fourth triggers n dklyucheny respectively to first and second outputs of the switching element, the first and second inputs of which form the input for application to the memory node, a second input of first OR input node is the initial installation.

3. The device pop. 1, which differs from the fact that the block of access to the central control unit contains three flip-flops, four AND elements and three OR elements, and the reset inputs of the first - third triggers are connected respectively to the outputs of the first - third elements OR, the first inputs of which are connected to the input of the initial installation of the unit, direct output of the second flip-flop co1

The invention relates to computing, in particular, to devices for interfacing the computer with external subscribers and can be used in automated control systems (ACS) operating in the time division mode.

The aim of the invention is to expand the class of tasks by organizing the exchange of arrays of information in the time division mode.

Figure 1 shows the block diagram of the device j in figure 2 - block diagram of the subscriber's subchannel; FIG. 3 is a functional block diagram of the circulation of a subchannel of a computer to a central control unit; Fig. 4 is a functional diagram of the memory access node of the central control unit; FIG. 3 is a functional diagram of a node for accessing the memory of a computer subchannel; Fig. 6 is a functional block diagram of a callback unit to the central control unit of the subscriber subchannel; Fig. 7 shows a functional diagram of the subscriber’s subchannel memory access node; Fig. 8 and 9 are connected to the first input of the first element I, the output connected to the first start output of the block and the installation input of the first trigger, the output of which is connected to the output of the block request and the first input of the second element I, the second input of the block connected to the reset input, and the output to the second inputs of the first and second MI elements and the second output of the block start, the second input of the first element I connected to the input of the block survey and the first input of the third elementAnd, the second input is connected to the inverse output of the second trigger, and the output to the polling output of the block and the first input of the fourth element AND, the output of which is connected to the installation input of the second trigger and the second input of the third element OR, and the second input the input of the block connected to the input of the request.

2

respectively, the functional diagrams of the priority of accessing all subchannels and the central control unit to the memory and all subchannels to the central control unit; 10 to 16 are examples of the implementation of functional diagrams of a computer subchannel exchange control unit, a node of a microprogram control unit of a central control unit, a trunk switching unit, a transition encoder, a subscriber subchannel exchange program microprocess control unit, a microprogram selection node and a transition encoder

Subchannel subscriber.

The device (Fig. 1) contains the exchange register 1, the exchange microprogram control unit 2, the modulo control unit 3, the OR 4 and 5 elements, the program readiness register 6, the subscriber subchannels 7, the unit 8 for accessing the central control unit of the computer subchannel, node 9 patterns to the memory of the central control unit, node 10 for accessing the memory of the subchannel of a computer, counter 11 of the address of the center block 313056984

control, address 12 of the signal control modes of the subchannel computer, trigger 13 occupancy RAM 21 (write or read). Central control unit, gene-10 stores (for 14 pulses, the second element of access to RAM 21) applications for subchannel 28, synchronization of applications and generation of the start signal of the RAM 21, as well as generation of control signals for the operating modes of the RAM 21 (Write or Read). Counter 11 provides for the formation of the addresses of the cells of RAM 21 when writing or reading information on the program readiness register 6. Numbered, memory occupancy trigger 24, elec- tic 12 provides for the formation of a delayed delay element 25, a trunk 26, a block of reses of the RAM 21 when writing or 27 central control (CU), under-f5 reading information to the register 1 channel 28 computer, computer 29, subscribers 30,

And 15 central control unit, the third element AND 16, the first element AND 17 of the central control unit, the first and second elements AND 18 and 19, frequency divider -20, memory block (RAM) 21, microprogram control unit 22 of the central control unit, unit 23 switching magistrantrigger 13 is designed to control the issuance of signals to the call center 27 and synchronize the operation of blocks of subchannels 7 and 28 when they are accessed

tires 31-83 connections between device blocks.

The exchange register 1 is intended for receiving, storing and issuing the address command and information words when exchanging with the computer 29.

Unit 2 provides the organization of the exchange of computer 29 with RAM 21 and with DD 27. With the help of module 3 of control modulo, the information received from computer 29 (provided in computer 29) is monitored, as well as information transmitted via highway 26. Element OR 4 combines all the start-up signals of the RAM 21 from the subchannels 7 and from blocks 9 and 10.

The element OR 5 combines all the sig30 of the RAM 21 is used to record, temporarily store and read information received from the computer 29 and subscribers 30 and entered into the computer 29 and subscribers 30 through the start code of the CPU 27, coming from the subchannels and the 8.35 Ral 26 block. The entire amount of RAM memory 21

The program readiness register 6 is separated into service areas and the worker secures temporary storage of the information word with signs for computer 29 to receive and / or send information, control the operation modes of subchannels 7 by transferring signs of the request to them, as well as forming an information word with signs

zone. Information from the service areas is used only to control the operation of the device. The number of service zones corresponds to the number of subchannels of 7 subscribers. In the first cell of each service area 21. subchannel

(i 1, n + 1) stores the starting address of the zone of the RAM 21 for forwarding information

performed by wok.

Subchannels 7 provide electrical and informational interface of subscribers 30, having various input-output interfaces, through RAM 21 and subchannel 28 with computer 29.

Block 8 provides storage (at the time of reference to DD 27) of the subchannel 28, synchronization of the request and

(i 1, n + 1) stores the starting address of the zone of the RAM 21 for forwarding information

45 from the corresponding subscriber 30 and the size of the received array. In the second cell of each subchannel zone, the starting address of the zone of the RAM 21 is stored for issuing information to the subscriber.

50 30 and the size of the array.

In the additional (n + 1) -th service area of RAM 21, the first to fourth cells store the corresponding generation of the start signal of the control unit 27. The node but informational words from the sign-. (Block) 9 store (on mobile computer 29) to receive information, the time of accessing the RAM 21) applications of the CO from subscribers 30 with the attributes of the request 27, synchronization of the application and the development of the computer 29 to issue information in the start signal of the RAM 21, as well as issuing nenty 30 with the signs of the hall 28, synchronization of the request and development of the start signal of the RAM 21, as well as the issuance of control signals Imami work RAM 21 (Write or Read). Counter 11 provides the formation of addresses of RAM 21 cells when writing or reading information to the program readiness register 6. Counter 12 provides the formation of addresses of RAM cells 21 when writing or reading information on register 1

The trigger 13 is designed to control the output of the signals to the DD 27 and synchronize the operation of the blocks of subchannels 7 and 28 when they are accessed.

to the CPU 27. The generator 14 pulses produces clock pulses, ensuring the operation of the device. The divider 20 generates by dividing the pulses of the generator 14 clock pulses

different frequencies for subchannels 7, since the exchange frequency of each of the subscribers 30 may differ from each other within wide limits (from tens of hertz to several megahertz).

RAM 21 is used to record, temporarily store and read information received from computer 29 and subscribers 30 and stored in computer 29 and subscribers 30 through code highway 26. The entire amount of RAM memory 21

divided into service areas and work

zone. Information from the service areas is used only to control the operation of the device. The number of service zones corresponds to the number of subchannels of 7 subscribers. In the first cell of each service area 21. subchannel

 divided into service areas and work

(i 1, n + 1) stores the starting address of the zone of the RAM 21 for forwarding information

45 from the corresponding subscriber 30 and the size of the received array. In the second cell of each subchannel zone, the starting address of the zone of the RAM 21 is stored for issuing information to the subscriber.

50 30 and the size of the array.

6 and subchannels 7 (double direction of tires. Functionally shown, receiving and issuing buses 40 are separate and independent from each other), bus

wok to receive information from subscribers 30 and with signs of completed requests for issuing information to subscribers 30,

The cells of the working area of the RAM 21 of the signal transfer time 21 The end of the work of the control center is stored (for the duration of the exchange) of the node 22, the control transmission bus 42, which is received from the computer or signals from the node 22, the output bus 43 subscribers 30. signaling

Node 22 provides for generation of subchannels 7, bus 44 for issuing a pulse sequence, determining -JO a request for RAM request from RAM embedded in its microprogram subchannels 7, bus 45 for issuing signals by mami. The unit 23 connects the register connection control to the rail 26 of the RAM 21, counters to the rail 26 (when recording addresses and registers of various units of the device in accordance with the control signals received on it. The trigger 24 is designed to control the output of the accessing the RAM 21 and synchronizing the work of reading or reading information), bus) 5 46 outputting control signals connecting the RAM 21 to the highway 26 (when writing or reading information), the bus 47 transmitting information between the RAM 21 and the highway 26 (dual channels 7 and nodes 9 and 10 when they access RAM 21. Delay element 25 delays the Start RAM signal in line 28 by the number of ticks ensuring the normal operation of RAM 21 from the start of writing the address into it until the start of writing (reading) the information word, and sends a delayed start-up signal to the line.

DD 27 consists of the element OR 5,

20, the direction of the tires is shown functionally, the buses 47 for receiving and issuing are divided and independent from each other).

25 The device also includes a signal transmission bus 48 Starting RAM, a delayed signal transmission bus 49 Starting a RAM, clock transmission bus 50, a sig.register 6 transmission bus 51, block 9, counter 11, Starting RAM trigger from block 9, a bus 52 hera 13, elements 15 and 17 and the signal transmission unit Starting up the RAM from block 10, bus 53 for transmitting control signals to counter 11 addresses, bus 54 for issuing addresses from counter 11, sew j to 55 sending control signals to register 6, bus 56 transmission of the information word with the signs for the computer booth 29 (or signs executed for the bill) I am waiting for register 6 and master. The device contains tires 31 pere p. 26, bus 57 signal transmission

22. The DD 27 provides the implementation of standard firmware for subchannels 7. The subchannel 28 of the computer consists of register 1, blocks 2, 3, 8 and 10 and counter 12. Subchannel 28 provides the exchange of information between the computer 29 and the device.

giving signals to control the operation of RAM 21 and block 23, signal transmission bus 32 End of operation of RAM, information transfer bus 33 between subchannels 7 and code trunk 26 (dual bus direction is shown functionally. Receive and issue buses 33 are separate and independent from each other) signal transmission buses 34 Starting RAM from subchannels 7, signal bus 35 Interrogating the presence of a bill to the CO, bus 36 signals Interrogating the presence of a bill to RAM, bus 37 transmitting signals Starting the MC, bus 38 clock pulses of different frequencies, bus 39 transmitting control signals node 22, tires 40 lane the presence of control potentials of the attributes of the computer filing and the signs of the subchannels 7 executed between the central control unit, the signal transmission bus 58 Starting the central unit from block 8 in the absence of the requisition from subchannels 7, the signal transmission bus 59 Starting the central control unit.

45 8, signal transmission bus 60 Stop CU from block 9, transfer bus 61 of the signal Start CU start from block 9, control signal transfer bus 62 from block 22, signal transfer bus 63 Op 50 increased in the presence of charge to RAM from block 9, a bus 64 of the address from the counter 12, a bus 65 for transmitting the control signals of the counter 12, a bus 66 for transmitting the signal +1 to the counter 12 of the address,

55 bus 67 signal transmission Application to the CU from block 2., bus 68 signal transfer Start from block 8, bus 69 transfer control signal from block 8, bus 70 transfer address from register 6 and subchannels 7 (dual direction bus. Functionally shown , buses 40 receiving and issuing divided and independent of each other), the bus

from subchannels 7, bus 44 issuing a signal Polling for transmissions to RAM from subchannels 7, bus 45 issuing control signals connecting registers and counters to trunk 26 (when recording

C or read information), the bus 46 issuing control signals connecting the RAM 21 to the highway 26 (when writing or reading information), the bus 47 transmitting information between the RAM 21 and the highway 26 (the dual bus direction is shown functionally, the bus 47 for receiving and issuing separated and independent of each other).

Start-up of the central control center, bus 58 of signal transmission Start-up of the central control center from block 8 in the absence of a charge from subchannels 7, bus 59 of signal transmission Start-up of the central control center.

45 8, signal transmission bus 60 Stop CU from block 9, transfer bus 61 of the signal Start CU start from block 9, control signal transfer bus 62 from block 22, signal transfer bus 63 Op 50 increased in the presence of charge to RAM from block 9, a bus 64 of the address from the counter 12, a bus 65 for transmitting the control signals of the counter 12, a bus 66 for transmitting the signal +1 to the counter 12 of the address,

55 bus 67 signal transmission Application to the CU from block 2., bus 68 signal transfer Start from block 8, bus 69 transfer control signal from block 8, bus 70 transfer address from the register 1 exchange to the address counter 12, bus 71 transfer modes operation, control signal transmission bus 72 from block 2 to exchange register 1, bus

73 receiving control signals to the unit holds (Fig. 12) triggers 205 and 206, 2 from computer 29, bus 74 issuing control switches 207, elements AND 208-210

signals from block 2 to computer 29, control signal transmission bus 75 to block 3, information control result transfer bus 76 to control unit 2, control signal transmission bus 77 from control unit 2j, signal transmission bus 78 Start from control unit 10, transmission bus 79 information from the register

element OR 211,

The cipher 191 transition contains (FIG. 13) a group of elements And 212, elements 0 213-218, a group of elements

RSHI 219, elements OR 220 and 221, elements NOT 222.

Firmware control unit 89

No exchange with the subscriber contains 1 in block 3, bus 80 receiving information f5 (FIG. 14), triggers 223-229, node 230 from trunk 26, microprogram selection transfer transfer 81, information counter 231 between register 1 and magic shifts, node 232 controls, elements of strike 26 (dual direction of tires and 233-244, elements OR 245-247, broadly shown, receive bus and receiver buses 81 are separated and independent from each other), bus 82 provides information to the computer 29, tires 83 receptions

here 248-256 intrablock connections.

Firmware selection node 230 contains (FIG. 15) decoder 257, counting 258, transition encoder 259, triggers 260 and 261, elements AND 262 and 263, elements OR 264-266, buses 267-271 intrablock connections.

 computer information 29.

Each subscriber subchannel 7 contains (FIG. 2) a block 84 for accessing the central control unit, a block for memory access 85, an address counter 86, a word counter 87, an exchange register 88, a subscriber exchange control program 89, a bus 90 103 links between subchannel blocks 7.

Block 8 of the reference to the central control unit of the computer sub-channel (fig.Z) contains triggers 104-106, elements 107 and 110, elements OR 111-113. Memory access node 9 contains (figure 4) triggers 114-117 elements And 118 -122, elements OR 123 and 124, switching element 125.

The memory accessing unit 10 contains (FIG. 5) triggers 126-129, AND elements 130-134, switching element 135, and OR elements 136 and 137.

Blocks 84 for accessing the CU contain (Fig. 6) triggers 138-140, elements AND 141-144, elements OR 145-147.

The memory accessing unit 85 comprises (Fig. 7) triggers 148-151, AND 152-156 elements, OR elements 157 and 158, and switching element 159.

Unit 2 of the microprogram exchange control with a computer contains (Fig. 10) triggers 160-169, elements AND 170-183, elements OR 184-188.

The microprogram control unit 22 contains (Fig. 11) a decoder 189, a counter 190, a transition coder 191, triggers 192 and 193, elements AND 193 and 195, elements OR 196-198, buses 199-204 of internal links.

Block 23 commutation trunk with. Element OR 211,

The cipher 191 transition contains (FIG. 13) a group of elements And 212, elements 0 213-218, a group of elements

RSHI 219, elements OR 220 and 221, elements NOT 222.

The exchange control microprogramme control unit 89 with the subscriber contains (Fig. 14) triggers 223-229, microprogram selection node 230, shift counter 231, control node 232, elements and 233-244, elements OR 245-247,

here 248-256 intrablock connections.

The firmware selection node 230 comprises (FIG. 15) a decoder 257, a counter 258, a transition encoder 259, triggers 260 and 261, elements AND 262 and 263, elements OR 264-266, buses 267-271 intrablock communications.

The encoder 259 of the transitions contains (Fig. 16) a group of elements AND 272, elements E 273-280, a group of elements LI 281, elements OR 282 and 283, and an element NOT 284.

The device works as follows.

When powering up

all blocks are reset. Trigger 13 implies a resolving potential at the inputs of elements And 15 and 17, and trigger 24 - a resolving potential at the inputs of elements And 16

and 18 and prohibiting the entry of elements AND 19. Subchannel 28 is ready to receive information and transmits readiness for exchange to .EV 29 via bus 74. There are no calls to RAM 21. Through element

And 16 to subchannel 7, the bus 36 receives the signals of the inquiry for the wok to the RAM. These signals sequentially interrogate all subchannels 7 (input 36 and output 44 buses), then blocks 9 and 10.

ZU .27 in its initial state generates signals of polling of requests to DD, which from the output of element 15 on bus 35 sequentially interrogate subchannels 7 (input 35 and output 43) and block 8. Since there is no flow to target 27, The start signal from the output of block 8 via bus 58 enters block 22 for installation on

It’s about the code, and through the elements OR 5, and 17 on the bus 57 to start up the work of the unit 22 according to the microprogram Preparation of subchannels 7.

Table 1 shows the algorithm of the device. After all the blocks of the device have been reset to their original state, the blocks A2, A5 and A7 begin to run simultaneously. Since there is no exchange with a computer 29 and there is no quotation for RAM 21, blocks A5 and A7 will constantly work on themselves.

If there are no bids to CU 27, block A3 is executed. Referring to CU, block A4 Preparation of subchannels 7. After the end of the A4 block operation and in the absence of the bill from the computer 29, the No branch of the A4 block passes to the A2 block, t. e. in the absence of an application for exchange from a computer 29, the availability of applications to DD 27 is constantly carried out, and in their absence, DD 27 executes the microprogram Preparation of subchannels 7.

In order for the device to begin work on the exchange of information with subscribers, in RAM 21 using a computer 29, all modes of operation of each subchannel 7 must be recorded (the values are received or / and received arrays, the initial addresses of zones 21 are high and / or reception, service information with signs for computer 29 for issuance and / or reception, as well as arrays of information words that need to be issued to subscribers 30).

In parallel with the operation of block A2 after exchanging with computer 29 on the branch there is block A5, block A6 starts to work, and then blocks A7 and A8. After the end of the recording in the RAM 21 along the branch PC 28, a transition is made to the input of the block A5.

The operation of the device with the computer 29 is carried out along the chain of blocks A5-A6-A7-A8-A5 until the computer 29 records in the RAM 21 the modes of operation of the device and all the arrays of information issued. Lastly, the computer 29 writes two informational words in RAM 21 with indications for reception and issue.

When executing the firmware Preparation of subchannels 7, these applications will be detected and transmitted to the corresponding subchannels 7 (A10 blocks). Subchannels 7, in which the applications of the computer 29 are rewritten for exchange, are exhibited

0569810

applications for accessing DD 27 for launching the firmware Start subchannels 7, Subchannels 7 will be sequentially launched. The operation of the device is carried out in the following sequence: block A2 - line IS - block A3 - block A4 - block A (10., - Yr) line For all RAM 21 and DD 27 - block A6 - line 0 to K DD 27 - block A2 - line IS - block A3 - line PK 7 - blocks A (10. - 10,). After subchannels 7 are consistently fired into. work, each of them can independently access RAM 21 for word-by-word recording (or reading) of information in the following sequence: block A10 - line Orders to RAM 21 and DD 27 - block A6 - block A7 - line There is from PC 7 - block A8 - lines PC-7 - block A10.

After subchannel 7 has completed the exchange with subscriber 30, it exposes a request to appeal to DD 27 to form a sign of the completed application. The operation of the device is carried out in the following sequence: block AID - line Orders to RAM 21 and DD 27 - block A6 - line C DD 27 - block A2 - line There is - block A3 - line PC 7.

The computer 29 periodically reads informational words with signs made for reception and for issuance in order to monitor the operation of the device, count the information received from subscribers 30, record new information in RAM 21 and issue new exchange applications.

20

25

The reading of signs of completed applications in computer 29 is carried out in the following sequence: block A5 - line Is - block A6 - line K

DD 27 - block A2 - line There is - block A3 - line PC-28 - block A12 - line Orders to RAM 21 and DD 27 - block A6 - line to RAM 21 - block A7 - line There is from PC 28 - block

A8 - lines PK-28 and block A5.

As can be seen from the device operation algorithm, all subchannels 7, 28 and DD 27 operate independently and in parallel. When executing various firmware (blocks A4, A9, A11, A12) of the target unit 27, the next zone of the RAM 21 is requested for the necessary information in the following sequence: the line of the Application to the RAM 21 and to the target center 27 11

- olok

There is from the CPU 27 - the CPU block 27 to the blocks A4, A9,

Block L6 - Line To RAM 2 A7 - Lirsh A8 - Line All, A12.

In parentheses of the tabl blocks, 1 shows the numbers of tables and fih ur, which describe the operation of the specified microprograms or function diagrams.

The entire operation of the device can be divided into separate stages:

preparing the device for operation (mode of receiving information from computer 29) including recording the initial addresses of reception zones and lengths and size of the transmitted arrays for each subchannel 7 in the cells of the service subchannel zones, recording information into the working zones of RAM 21 for those subchannels that are to output information in subscribers, recording of two information words with signs for computer 29 at the reception and in the first two cells of the additional service area of the RAM;

Execution of TC 27 firmware Preparing subchannels

Execution of TC 27 firmware Start subchannels

Execution of the firmware 27 of the microprogram. Formation of signs of fulfilled requests;

execution of the CO 27 firmware; Issuance of signs executed by the request;

the operation of the device in the mode of issuing information in the computer 29;

device operation in the exchange of information between subchannel 7 and subscriber 30.

The device is prepared for operation by a computer 29. It is as follows: Computer 29 receives two information words, which are recorded in the first two cells of the service area of RAM 21 of the first subchannel, then computer 29 receives the following two information words, which are written in the first two channels cells of the service area of RAM 21 of the second subchannel, then of the third and t, d., until two cells of the zone of RAM 21 of the last subchannel are filled,

The first cell of the service area of the RAM 21 always records the starting address of the information receiving zone from the subscriber 7 and the size of the received array. The second cell of this zone is always recorded with the start address of the zone.

0569812

There are information in the subscriber 7 and the size of the output array.

Thus, the computer 29 pre-distributes the RAM 21 to the working reception areas and information delivery areas for each subchannel 7, through which information will be exchanged with subscribers 30.

After the recording of the information O in the service areas of the RAM 21, the computer 29 records, in the working area of the RAM 21, the information that the device must transmit through the subchannels 7 to the subscribers 30, the information in the working area 5 is recorded in accordance with the initial addresses of the issue zones of each subchannel 7 ,

At the last stage of preparing the device for operation, the computer 29 records 20 information in the first two cells of the additional service area of RAM 21,

In the first cell of the additional service area, an information word is recorded with the signs for a computer 29 to receive information by the subscriber 30, and the second is an information word with signs for a computer 29 for issuing information to subscribers 30,

At the same time, each of the subchannels 7 corresponds to a pre-determined bit of the information word, in which there is a sign of an application for the exchange of a QT computer 29 with specific subscribers through subchannels 7,

35 At this, the preparation of the device for the exchange with the subscribers 30 according to the computer program 29 is completed.

The same preparation of the device for exchange with subchannels 7 can be

40 is carried out by the computer 29 at any time after the computer 29 determines that the device has completed the exchange of information with one or several subscribers.

25

thirty

45

Since DD 27 executes the Microprogram Preparation of Subchannels of Subscribers cyclically, after recording information words with signs of a request for an exchange, Exchange 27 will detect these requests and begin to execute the firmware of the subchannels. When performing the mode of issuing information to the subscriber 30, subchannel 7 reads information55 from the working area of the RAM 21 in accordance with the specified starting address of the zone and the size of the array located in the second cell of the service area of the RAM 21.

the mode of receiving information from the subscriber 30f, subchannel 7, writes the received information into the working area of RAM 21., in accordance with the initial address of the reception area and the array size j located in the first cell of the area of RAM 21a.

If the computer 29 received applications for receiving and issuing with the subscriber at the same time, the device organizes the operation of subchannel 7 for information, first, and after the output mode ends, for receiving information from the subscriber.

After the end of the exchange (by receiving 5 or: and issuing information), subchannel 7 outputs to the control center 27 a signal for ending the exchange with the subscriber. On this signal, in block 22, the microprogram is turned on. Formation of a sign of completed 20 applications.

The information word with the signs of the computer 29 performed by the computer to receive information from the subscriber 30 of the recorded area of the RAM 21 and controls the progress of the request. As required, after the device completes the order, the computer 29 exchanges in the RAM 21 HOBbie arrays of information and new applications for the exchange. The operation of the computer 29 with the RAM 21 through the subchannel 28 and the operation of the subchannels 7 with the RAM 21 are performed in parallel in the time division mode.

Consider the operation of the interface when receiving information in the RAM 21 from the computer 29.

On the computer 29 B, the beginning of the exchange is always the first to receive the address command with signs of the operation mode of the subchannel 28 and the starting address of the zone of the RAM 21, where information will be recorded (in the mode of computer output).

The address command from the computer 29 is transmitted via bus 83 to register 1. Block 2 analyzes the characteristics of the address command and the exchange mode received on bus 71. After receiving the address command

 always in the third cell, add-block 2 via bus 65 generates a signaling service zone of RAM 21, and a cash on which the starting address for an information word with signs above 70 from register 1 rewrites the filled-in applications for computer 29 c into the counter 12. At the same time, the formation block into the subscriber 30 — always on an even-2 — issues a readiness signal in the computer on the top of the additional service -30 bus 74.

to each of the subchannels 7 corresponds to a predetermined cell size, into which the sign of the recording performed from a particular subchannel 7 is recorded. The device provides multiplex operation of all subchannels 7, 28 and DD 27 with RAM 21, i.e. . Each of the subchannels 7 works independently after receiving a signal on the device operation pressures on the bus 42, therefore, the launch of the subchannel from the CO 27. The subchannel 28 can organize an exchange with the computer 29 at any time and receive the next information words with signs exchange information with computer 29 when it is accessed and receive regular information words with the characteristics of the request for exchange and information for issuing to the subscriber or output information words into the computer 29 with the characteristics of the requests made and information received from subscribers 30. DD 27 at this time executes its firmware for applications from one of the subchannels 7 or 28.

The computer 29 periodically reads informational words from the third and fourth cells of the additional service area of the RAM 21 and monitors the progress of the application. As required, after the device completes the order, the computer 29 exchanges in the RAM 21 HOBbie arrays of information and new applications for the exchange. The operation of the computer 29 with the RAM 21 through the subchannel 28 and the operation of the subchannels 7 with the RAM 21 are performed in parallel in the time division mode.

Consider the operation of the interface when receiving information in the RAM 21 from the computer 29.

On the computer 29 B, the beginning of the exchange is always the first to receive the address command with signs of the operation mode of the subchannel 28 and the starting address of the zone of the RAM 21, where information will be recorded (in the mode of computer output).

The address command from the computer 29 is transmitted via bus 83 to register 1. Block 2 analyzes the characteristics of the address command and the exchange mode received on bus 71. After receiving the address command

Block 2, via bus 65, generates a signal at which the starting address on bus 70 from register 1 is rewritten to counter 12. At the same time, block 2 issues a ready signal to the computer via bus 74.

In response to this signal, the computer 29 issues the first information word over bus 83 to register 1. Block 2 removes the ready signal for the computer 29 and outputs 35 a signal to the application to the RAM via bus 77 to block 10.

Appealing to RAM 21 to write or read any of the subchannels 7, 28 or DD 27 - one of the main we consider the algorithm of operation of the device when accessing the AMS 21, shown

in table.2. one

When operating subchannel 28 with RAM 21, the address of the RAM cell is always indicated by a counter 12, and the write (read). the information word is carried out from register 1 via code line 26.

When working with the RAM 21 of one of the subchannels 7, the address of the RAM cell is indicated by the counter 86 of that subchannel 7, which refers to the RAM 21, and the information word south is written (read) through the register 83 of that subchannel 7, which refers to the RAM 21.

When working with RAM 21, the CPU 27 can use not only its own 1 1 1 address and 6 register of program readiness, but also 86 addresses of the address and 1-88 exchange of subchannels 7 and 28.

In accordance with the algorithm for accessing RAM 21, the first word of information from register 1 will be written in

DD 27 works simultaneously with under

RAM 21 at the address set by channel 10 and 7 and 28, which are on the counter 12 at that time. Signal The end of work of RAM, issued via bus 32, is reset in block 10 for RAM 21. Signal Start, started by node 10 bus 78, recovers in block 2 a signal of readiness of the subchannel 28 to work with a computer. At the same time, block 2 outputs via bus 66 a signal to modify counter 12, i.e. the address of the next RAM 20 is set.

m are sharing with subscribers 30 and computers 29.

Basically, the task of the CO 27 is to execute the firmware for transferring the signs of the filing of the computer 29 to subchannels 7, to set the modes of operation of the subchannels 7 and to put them into operation. Upon completion of the exchange of subchannels 7 with subscribers of the COU 27 (according to the application of subchannels 7), it forms informational words with signs of the requisition performed. When the computer 29 accesses the device, the words with the signs of the following request of the CPU 27 according to the microprogram organize the output of these words to the subchannel 26, which then issues them to the computer 29.

After receiving the signal g of the device’s compliance via bus 74, the computer 29 outputs to register 1 the following information word, which will be similarly written to the next cell of RAM 21.

After receiving from the computer 29 the last word of information on register 1 and recording it in the RAM 21, the computer 29 outputs to the device an end-of-bus signal 73. With this signal, all units of the computer subchannel 28 are reset. At this point, the operation of the device in the mode of transmitting information from the computer 29 to the RAM 21 ends.

To record information in the zone of issue of another subchannel 7, the computer 29 again issues an address command with the starting address of the zone of this subchannel. The starting address is transferred to counter 12. The first word received from computer 29 will be recorded in RAM cell 21 at this address. By the signal of the end of the operation of the RAM 21, the address in the counter 12 is incremented by one, and the received next word of information from the computer will be recorded in the RAM 21 at the new address. When the recording of information into the zone of issue of the RAM 21 is completed, the computer 29 outputs a signal to the device at the end of the exchange and the computer subchannel 28 is reset.

Information from a computer 29 is also recorded in a similar way to the zone of issue of other subchannels 7, as well as two information words with features. Computer 29 to receive information from

569816

subscribers and signs of computer charging for issuing information to subscribers. The call to the CO 27 of the subchannels 7 and 28 to execute a certain 5 pre-firmware is performed as follows. Consider the work of DD 27 according to the algorithm given in Table. 3

DD 27 operates simultaneously with sub-10 channels 7 and 28, which at this time is 5 0

five

0

five

0

five

0

m are sharing with subscribers 30 and computers 29.

Basically, the task of the CO 27 is to execute the firmware for transferring the signs of the filing of the computer 29 to subchannels 7, to set the modes of operation of the subchannels 7 and to put them into operation. At the end of the exchange of subchannels 7 with the subscribers of Cal 27 (according to the application of subchannels 7), it forms informational words with the signs of fulfilled requests. When the computer 29 accesses the device, the words with the signs of the following request of the CPU 27 according to the microprogram organize the output of these words to the subchannel 26, which then issues them to the computer 29.

Consider the operation of the interface device according to the firmware of the CO 27. Preparation of subchannels 7 according to the algorithm given in Table 4.

In the initial state, the blocks and elements of the DD 27 are set in such a position that the node 9 is in the zero state, the program readiness register 6 and the address counter 11 are in the same state, the resolving potential at the inputs of the AND elements 15 is at the output of the trigger 13. and & 17.

The frequency from the output of generator 14 via bus 50 enters the input of the element I 15 and from its output, as signals from the inquiry to the CO, via bus 35 goes to subchannel 7, if there is no flow to the CPU 27 in subchannel 7, the polling signals the order goes through buses 43 and 45 to the next subchannel 7, and so on. If there is no quotation in any of the subchannels 7, then the polling signal of the quotation enters via bus 43 in block 8.

If there is no application in block 8, then the request polling signal from the output of block 8 is sent via bus 58 to the input of node 22 to set the microprogram code -5 Preparation of subchannels 7 and to the input of the OR 5 elements.

From the output of the element OR 5, the signal of questioning the request as a start signal

17

through the element 17 on the bus 57 enters the trigger input 13 and sets it to one. With the release of trip-erra 13, a potential begins to be issued that will prohibit pro

Signal Survey

13056

TsU through the element And 15 and the start signals through the element And 17.

When a signal is received, the start of the CU; el 22 begins to generate a sequence of pulses in accordance with the M1 :: subprogram Preparation of subchannels 7.

Firmware The preparation of subchannels 7 is executed by DD 27, when there are no applications to DD 27 from subchannels 7 and 28, as well as applications from subchannels 7. The essence of this firmware is as follows, DD 27 reads two information words from RAM 21 in turn signs for the computer 29 to receive and to issue, which are recorded in the register 6. From register 6 on tires 40, signs for the computer 29 are transmitted to subchannels 7. First, the applications for the call to the reception and then to the issue are transmitted.

Subchannel 7, having received these acknowledgments, file their applications for appeal to DD 27.

If the computer 29 did not write into the cells of the RAM zone 21 two information words with signs of a quotation, then the register

6 will be read zero information and, therefore, in the subchannels

7 also zero signs will be transmitted, i.e. subchannels 7 will remain

in the initial state.

After the attributes of the order of the computer 29 are rewritten into subchannels 7, the blocks 84 of these subchannels 7 are put into operation by the termination signal of the output of the CO 28 via bus 41. Those subchannels 7 that received the signs of the exchange of the computer 29 exchanged calls to the MC to run the firmware Start subchannels 7.

t

Under this firmware, subchannels 7 (sequentially, in accordance with their priority) will read the information words from the cells of the service areas of RAM 21 with the initial addresses of the issuing or receiving zones and the size of the arrays issued or received. At the end of the firmware execution, the start of subchannels 7 from DD 27 issue5

5698

signal start in the work of subchannel 7.

Let, for example, the first subchannel 7 received (after the execution of the microprogram Preparation of subchannels 7) a sign of the application for issuing information

per subscriber 30. With the firmware of the CPU 27 Starting subchannels 7, the first subchannel 7 from the second cell of the first service zone of RAM 21 will read the word in which the starting address of the working zone 05У 21- is indicated, i.e. the first address, starting with which the information should be output to subscriber 30 and the size of the output array, i.e. the number of words issued. Receiving a start signal from DD 27, the first subchannel 7 begins to sequentially read the words from RAM 21 and transfer them to subscriber 30.

20 Consider the execution of the CPU 27 firmware Start subchannels 7 according to the algorithm given in Table 5.

15

After the execution of the microprogram Start subchannel in the address counter 86 and the counter 87 words of subchannel 7, the address of the first cell of the working zone of the RAM 21 and the value of the received (received) array are set.

DD 27 drives the start signal of the first subchannel 7 via bus 42, which starts operating according to its firmware. If the application is set up for information, then subchannel 7 refers to RAM 21 for reading the first word of information. The algorithm for accessing RAM 21 is shown in Table 1. After reading the first word of information on its exchange register 88, it is organized to issue it to the subscriber 30 in accordance with the requirements of the subscriber's I / O interface. If the first subchannel 7 has a request for receiving information, it organizes receiving one word from the subscriber 30 and calls the RAM 21 to record a word of information at the address set on the counter 86 of the address of subchannel 7.

The issuance or reception of the remaining informational words is carried out similarly.

The launches and operation of the remaining subchannels 7 are similar, but each of the subchannels works with subscribers in accordance with the requirements of its I / O interface.

After the end of the exchange with the subscriber, the subchannel 7 exposes the subscriber to the call to the CO 27 via the bus 37 and simultaneously on the bus 39 transmits signs of the end of the exchange. According to this application, MC 27 begins to execute the firmware. Formation of signs of completed requests. According to this firmware, informational words are formed with acknowledgment of the request for admission and issuance. The work of the kami performed for the reception and the device in the mode of issuance in the computer 29 on the issue. These words are recorded in information with signs of pre-determined additional overhead area of RAM 21, from which the computer 29 reads them periodically. - mu in table 7.

The same firmware is used to cancel the signs of the application of the computer 29 after the exchange between subchannel 7 and the subscriber. If the information was sent to subscriber 30,

The request for acceptance and delivery is carried out according to an algorithm, reduced to 20

Since the work of subchannels 7 and 28 is carried out in the time division mode, the exchange with the computer will occur in parallel with the work of the subchannels 7.

From computer 29, bus 83 enters register 1 with the address-command with a sign that the information words are read, in which the signs for execution of the necessary functions contain signs of completion

novok Block 2, on the basis of the signs received in the address command, sends over bus 39c. Signs of the operation of node 22 and bus 67, submission of DD 27 to block 8. 30 Block B issues a start signal on node 59 of node 22, which starts to execute the microprogram Signs of signs performed by the wok. The essence of the device for this firmware

then it quits for computer 29 to power. If the information was received from subscriber 30, then quits for computer 29 to receive

thread so as not to cause a false start of subchannel 7 for the application that has already been completed.

Consider the operation of the device by firmware. Formation of signs of completed orders in accordance with the algorithm given in Table 6,

As already noted, all subchannels of the device operate in time-sharing mode; therefore, in the absence of the quotation to the CO 27 from subchannels 7, the polling from the quotation to the CO from the output of the And 15 element passes successively through all the subchannels 7 and sets the code on the bus 58 in block 22 the start of the microprogram Preparation of subchannels 7. At the same time, the same signal passes through the elements OR 5 and 17, as the start signal of block 22 via bus 57. The microprogram Preparation of subchannels 7 begins.

After the execution of this firmware, the exchange modes of the subchannels 7 that have changed the exchange direction will be confirmed. The work of those subchannels that have not completed their exchanges with subscribers is not influenced by microprogramming Subchannel Preparation 7. At the same time, in those subchannels 7, in which the exchange mode change was confirmed and the exchange request received in the new mode, 35 was to prepare for the issuance to the computer 29 two words of information with the signs of the requisition and reception requests that are in the third and the fourth cells of the additional service area of the RAM 21. After the firmware has been executed and the readiness signals for exchange with the computer 29 are restored, the device

45 (subchannel 28) is waiting for the exchange to continue, i.e. The computer 29 must read the word with the signs of fulfilled quotation (at the reception) from register 1.

Upon completion of this readout, block 2 adds a unit to counter 12 via bus 66, removes readiness signals to exchange with computer 29 and sends, through bus 77, the signal to access RAM 21 to node 10. Access to RAM 21 on

55 information is read through bus 52 from node 10. The word with the signs executed for the request (for issue) will be read from the first cell (counter 12 is the first address)

Ie, the application is submitted for appeal to well 27. According to this application, MC 27 will start to execute the microprogram Start subchannels 7, after which the subchannel will receive a start signal from DD 27 for another exchange with subscriber 30,

The computer 29 periodically turns to the device and reads two words of information with signs of

for wok at the reception and to issue. The operation of the device in the mode of issuing in the computer 29 information with signs executed

Table 7.

The request for acceptance and delivery is carried out according to an algorithm, reduced to 20

in preparing for issuing to computer 29 two words of information with signs performed for reception and for issuance, which are in the third and fourth cells of the additional service area of RAM 21. After the firmware has been executed and restored readiness signals to exchange with computer 29, device

(subchannel 28) expects the exchange to continue, i.e. The computer 29 must read the word with the signs of fulfilled quotation (at reception) from register 1.

Upon completion of reading this, the spruce block 2 adds a unit to the counter 12 via bus 66, removes readiness signals for exchange with the computer 29 and sends the call signal to the RAM 21 to the node 10 on the bus 77.

the information is read out via bus 52 from node 10. The word with signs executed for the request (for issue) will be read from the first cell (counter 12 is the first address)

211

through highway

working area of RAM 2 26 in reg istr 1.

The RAM 21 generates a signal. The end of the RAM, which sets the block 10 to its initial state via the bus 32. The signal from the output of block 10 via the bus 78 in block 2 restores the readiness signals to exchange with the computer 29. The computer 29 reads the word with the signs A wok (for output) and outputs into sub subanap 28 a signal for terminating a ziin exchange 73. The blocks of subchannel 28 are set by this signal to their original state. On the bus 74 in the computer 29 signals of readiness of the device for exchange are transmitted.

After analyzing the performed back-up computer 29, according to its program, it writes new arrays of information into the device and issues new applications for exchange with subscribers 30. At the same time as subchannel 28 and DD 27 work, subchannels 7 exchange information with subscribers 30. Consider the operation of the device when exchanging information between subchannel 7 and the subscriber 30 according to the algo- given in table.8.

The mode of information input to the subscriber 30 is carried out in the following sequence: B1-B2-BR3 (B4-B8) -B9-B10-B15.

The mode of receiving information from subscriber 30 is carried out in the following sequence: B1-B2-BZ-B4- (B11-B14) -B9-B10-B15.

In subchannels 7 (FIG. 2), address counter 86 is used to form the address of cells when writing to RAM 21 (or read from RAM 21) information words received from the subscriber (or output to the subscriber). The word counter 87 counts the words received from the subscriber (outputted to the subscriber) and the generation of an exchange termination signal with the subscriber. The exchange register 88 provides for the transfer of information words between the RAM 21 and the subscriber 30.

Block 89 is intended to form a timing diagram of the exchange of information between the subscriber 30 and RAM 2

Signal communication buses with block 89 are as follows: signal transmission bus 90 Application to the CO, signal transmission bus 91 Start 1 of block 89, control signal transmission bus 92 to address counter 86 and word counter 87, signal transmission bus 93

eight

22

yes counter 86, bus 94 signal transmission overflow, bus 95 transmitting the address code from register 88 to counter 86, bus 96 transmitting the code

the size of the array of information from the register 88 exchange in the counter 87, the bus 97 issuing information from the register 88 exchange in the subscriber, the bus 98 receiving information in the register 88 from the subscriber,

bus 99 of transmission of shift pulses, bus 100 of signal transmission Setting to the initial state, bus 101 of signal transmission Application to RAM, bus 102 of transmission of signal Start 2

block 89, bus 103 signal transmission Stop in block 89.

When the supply voltages are turned on, the signal 100 is supplied via the cord 100. The installation returns to the initial state, according to which all the blocks of subchannel 7 are reset.

On bus 35, block 84 receives signals from the inquiry to the CO, but since there is still no inquiry to the CO, these same signals are output from block 84 to the bus 43.

Signaling a request for RAM to RAM enters unit 85 via bus 36, but since there is still no request for RAM 21, the same signals are output from block 85 to bus 44.

The bus 38 receives the clock pulses of the frequency at which the subscriber 30 operates.

Subchannel 7 operates as follows.

By Firmware Preparation

subchannels 7 to block 89 on the bus

(from register 6 of program readiness)

Signs are recorded for the computer's wok.

exchange.

If there is no quotation, then the subchannel will remain in its original state.

After installation in block 89

a bus signal is received for exchange via bus 42 from DD 27, through which block 89 starts operating. From its output via bus 90, the Signal of Request signal to DC comes into block 84. This application will be

detected by the next signal Interrogation of the request to the central control center (via bus 35) and from the output of block 84 through the bus 37, the start signal of the central control center will be given. At the same time, the same signal arrives at block 89 and stops its operation. HU 27 will begin to execute the firmware. Starting up the subchannels 7. When you run this firmware into register 88, bus 33 will read the word from RAM to

the initial address of the reception area and the size of the received array (if the computer is processed to receive information from the subscriber) or with the initial address of the zone of issue and the size of the issued array (if the computer is executed for issuing information to the subscriber). Then, the starting address is rewritten from register 86 via bus 95 to counter 86, i.e. the address of the first cell will be assigned, where it is necessary to record the first word (at reception) or cancel the word, and it is necessary to count the first word (at issue).

From register 88 via bus 96 to counter 87, the size of the array (word count code) to be received or output is rewritten. Transmission from register 86 over busses 95 and 96 is effected by the control signal outputted by block 89 over bus 92.

After the completion of the microprogram Start-up of subchannels 7, bus 41 receives an end-of-operation signal from DD 27, which resets the request from DD in block 84 and is outputted on bus 91 as a signal from Start 89 of block 89. Blo 89 analyzes the behavior of the subchannel. If a computer was received for receiving information from subscriber 30, then block 89 organizes the reception of one word from subscriber 30 to register 88 via bus 98. After the word is received on register 88, block 89 sends a signal to Bus 101 to RAM. In block 86, a request will be set for reclaiming RAM 21. The request will be detected by the next request for RAM request (bus 36), the bus 103 will give a signal to stop the operation of block 89. In RAM 21 the address of the first cell will be recorded the first word in the working area of reception of RAM 21 ,,,

The termination signal of the RAM 21 over the bus 32 in block 85 will be reset to RAM and the Start 2 block of block 89 will be reset via bus 102. Block 89 sends out a signal 92 through bus 92 to counters 86 and 87, i.e. the address of the second cell of the working area of RAM 21c and the second word will be set. After that, block 89 organizes the reception of the second word from the subscriber.

Similarly accepted

all subsequent words. After the last word is written to the last cell of the RAM 21k reception area, the counter 87 generates a warning signal on bus 94, Block 89 will change the characteristics of the operation mode performed on bus 39 to DD 27 (it indicates the end of work with the subscriber), and one by one bus 90 sets in block 84 for CC

According to this application, MC 27 will begin to execute the firmware. Formation of signs of fulfilled requests.

The control signal of the executed request (reception) sign is output from block 89 via bus 40, to register 6 of program readiness.

If the request was received for the computer 29 for the delivery of information to the subscriber 30, then block 89 passes the 101 to the RAM message on bus 101. In block 85, the application will be installed on the appeal to the RAM 21 at the address of the first cell (installed on the counter 86). The request will be detected by the next signal Survey of the request to RAM (bus 36), and the bus 103 will give a signal to stop the operation of block 89. The first word will be read from the first cell of the RAM issue zone 21 to register 88.

The termination signal of the RAM 21 over the bus 32 in block 85 will be reset to RAM and a Start 2 signal from block 89 will be given via bus 102. Block 89 sends a +1 signal to counters 86 and 87 via bus 92, i.e. the address of the second cell will be set to read the second word. After that, block 89 organizes the issuance of the information word from register 88 on tires 97 to subscriber 30.

Similarly, all subsequent words are displayed.

After the last word is issued, the scratch 87 on the bus 94 generates an overflow signal, according to which the block 89 via the bus 90 exposes the customer to the call center 27. On the bus 39 a sign of the end of the exchange with the subscriber will be displayed.

HU 27 will begin to execute the firmware. Formation of signs of completed orders. The control signal of the executed request (for issue) sign is output from block 89 via the 40t bus to register 6.

In block 8 (FIG. 3), trigger 10A provides storage of the application for the operating time of the DD 27. The trigger 105 controls the passage of the signals from the Questionnaire to the DT through the elements 107 and 109.

The trigger 106 is intended for the sync signals sent to bus 67. In the initial state, the triggers 104-106 are set to the zero state on the bus 100, respectively, through the OR elements 111-113. potentials, respectively, at the inputs of the elements And 108 107 and 110.

Block 8 works as follows

The request polling signal to the CO comes on bus 43 and passes through AND 109 to bus 58. When accessing CO 27, the signal for block 2 enters bus 67 and sets trigger 106. A trigger potential will be output from trigger output 106 on the element and 110.

The following. The request for quotation signal from the bus 43 passes through the elements 109 and 110 and sets the trigger 105. At the same time, the signal from the output of the element AND 109 enters the bus 58. From the output of the element 110 and through the element OR 113, the trigger 106. The next signal, the inquiry to the central office (this sy :: the wave goes with the frequency generated by the generator 14) passes through the element 107, opened by the resolving potential from the output of the trigger 105, to the bus 59, as the start signal of the central unit (node 22) and at the same time to the installation of the trigger 104. From the output of the trigger 104 will start issuing Avoid the resolving potential to bus 69, i.e. for VKA. Since the start signal was set up on the 59 bus and the 27 CU started to work, then the bus 43 will stop receiving signals.

After the node 22. finishes the execution of the microprogram, it will generate an operating signal. This signal from the bus 41 passes through the AND 108 element opened by the resolving potential from the output of the trigger 104. From the output of the AND 108 element, the signal ending in the work passes through the elements SH1L 111 and 112 and sets the triggers 104 and 105 to the initial state. At the same time, the end of work signal goes to bus 68 as a start signal of unit 2. Block 8 is ready again

to take the signal for vki. |

On the bus 43 again will begin to flow

Signals Poll Quotes to CC. At node 9, trigger 114 provides storage

application to the GTM on the operating time of the RAM 21 and generates on the bus 31 potential for applications to the input of the block 23.

Tp 1ter 115 controls the passage through .elements And 118 and 121 signals Survey for RAM. Trigger

116 generates a control signal of the nature of the access to RAM 21 (write or read) and issues it via

element 120 on the bus 31. The initial state of its corresponds to the record, and the opposite - to read from the RAM 21. The trigger 117 is intended to synchronize the signal of the request posting on the bus 62.

In the initial state, the flip-flops 114117 are set to the zero state on the bus 100 through the elements OR 123 and 124. From the outputs of the flip-flops 114,

116 and 117 and from the direct output of the trigger 115, the prohibitive potentials are output to the inputs of the elements AND 119, 120, 122 and 118, respectively, and from the inverse output of the trigger 115, the input permitting element AND 121.

Node 9 works as follows. Interrogation signals from the request to RAM 21, received via bus 44, pass through AND 121 to bus 63. Bus 62 receives a signal to RAM 21 to write (line 62) or a request signal to read (line 62) . The signal for recordings is sent only to the input of trigger 117 through the element

125 switching, and the signal for reading applications is set through switching element 125 to the input of trigger 117 and to the input of trigger 116. The next polling signal for the wok with

bus 44 passes through the elements AND 121 and 122 and sets the trigger 115. At the same time, from the output of the element AND 122, the signal through the element OR 124 sets to the initial state the trigger

117. The trigger 115 will begin to issue the permissive potential on the element And 118 and the prohibiting potential - on the input of the element 121.

The next poll signal passes

through the element 118 on bus 51, as a signal Zusk RAM, and on bus 60 as a signal to stop operation of the DD 27. At the same time, a trigger 114 is set, from whose output it will begin

increase the resolving potential to both the 119 and 120 elements and the bus 31.

If a call is made to write information to the RAM 21, then with

27

And 120 will come to the bus 31 with a zero potential (the type of circulation is writing). If rotation is performed to read information from RAM 21, then from the output of the element 120 120, a single potential is given to the bus 31 (the character of handling is reading).

The following polling signals of the quotation to RAM along bus 44 will not arrive, as RAM 21 is busy.

After the end of writing (reading) of the RAM 21, it issues an end-of-work signal, which is fed along bus 32 through AND 119 to bus 61 (as a start signal) and through OR 123 to reset the triggers 114-117. The RAM access unit is ready to accept a new application. Signs of demand for demand will again start arriving on bus 44, as RAM 21 has finished its work.

In block 10, in the initial state, the triggers 126-129 are in the zero state. From the outputs of the flip-flops 126 129, the inhibitory potentials are given to the inputs, respectively, of elements And 131, 134 and 130, and the permitting potential at the input of element I 133. C: - search polls for quotation. RAM is fed through bus 63, passes through element 11 and 133 , but do not proceed further, since the element And 134 is closed by the inhibitory potential from the output of the trigger 129.

Block 10 works as follows.

Upon receipt of the application for writing into RAM 77, the trigger 21 129 will be set to one. The trigger 128 will remain in the initial state (the character of circulation is written to RAM), since the inhibitory potential flows through the bus 77.

When the resolving potential arrives on the bus 77 at the input element I 135 (read from RAM 21) by a signal from the bus 77, the triggers 129. and 128 will be set to one state. From the output of the element I 132, a resolving potential is issued (the character of the circulation is the reading). The polling signal from the bus 63 through the elements And 133 and 134 sets the trigger 127, and

Next polling signal for wok

the cut element OR 137 - to the initial junction 35 passes through the elements AND

stand trigger 129.

The next interrogation signal passes through the element I 130 to the bus 52 as a signal to start the RAM and simultaneously to

143 and 144 at the input of the trigger 193 and at it turns off. Simultaneously, the signal from the output of the element And 143 enters the bus 43, and from the output of the element And 144

0

five

0

698

28

trigger input 126, setting it to one, i.e. set for the PU.

Cigars on bus 63 will not be received, since RAM 21 is busy. The resolving potential from the trigger output 126 is fed to the inputs of the And 131 and 132 elements, as a signal to the bus 3 1f.

From the output of the element 132 on the bus 31 lr, the potential of the nature of the call (prohibiting writing to RAM, permitting reading from RAM).

After the RAM 21 is accessed (to write or read), the RAM 21 issues an end-of-work signal, which is sent via bus 32 through AND 131 to bus 78 as a start signal, and through OR 136 to initialization of all triggers 126-129.

The bus 63 will begin to receive the polling signals for the wok to the RAM, since RAM 21 has finished its work.

Unit 10 is ready to receive the stock.

In block 84 (Fig. 6), trigger 138 provides storage of applications for the operating time of TC 27, trigger 139 controls the passage of Signals Polling applications to DD through elements 141 and 143. Trigger 140 is designed to synchronize the request received via bus 90 Along the bus 91, a Start 1 signal is issued.

In the initial state, the triggers 138-140 are set to the zero state on the bus 100 via the elements OR 145-147.

five

0

five

From the outputs of the flip-flops 138-140, the prohibitive potentials are given to the inputs of the And 142, 141 and 144 elements and the permitting potential for the input of the And 143 element.

Block 84 operates as follows.

Signals The inquiry to the CO from bus 35 passes through AND 143 to bus 43. The request goes through bus 90 and sets a trigger 140, from which output a permitting potential per I 144 will begin.

The next polling signal for the wok

35s passes through the elements and

bus 35 passes through the elements and

143 and 144 at the input of the trigger 193 and sets it. At the same time, the signal from the output of the element And 143 is fed to the bus 43, and from the output of the element And 144

The OR element 147 sets the trigger 140 to the initial state. The next request polling signal from bus 35 passes through the AND 141 element, opened by the resolving potential from the trigger output 139, to the bus 37, as a start signal of the central control unit, and simultaneously to the set trigger input 138 , which will begin to issue the resolving potential to the bus 40. On the bus 40, the equipotential potential arrives at the entrance of the register 6 of program readiness. When the firmware 27 is executed by the Formation of signs of the executed requests, this control potential will solve the recording of the sign of the application executed in register 6.

The control potential from the bus 40, from the subchannels 7, is connected to the input of a certain bit of register 6, i.e. The sign of the request from the first subchannel is recorded in a pre-determined register bit 6. For example, from the first subchannel 7, the sign of the executed request is recorded in the first register bit 6, from the second in the second, etc.

The following interrogation signals of the request to input 35 are not received, since DD 27 is occupied by the execution of the corresponding microprogram, after which the signal on the bus 41 enters the input of the AND 142 element, opened by the resolution potential from the trigger output 138. From the output AND 142, the completion signal passes through the OR elements 145 and 146 and sets the triggers 138 and 139 to the initial state. At the same time, the end of work signal from the output of the And 142 element is fed to the bus 91 as the Start 1 signal. Block 84 is ready to receive a new application. The bus 35 will again begin to receive the polling signals of the request, as the CO has finished its work.

Fig. 7 shows the functional diagram of block 85, which takes the memory access request via bus 101 (101 - to write, 101 - to read). Bus 102 provides a Start 2 signal to block 89, and bus 103 receives a Stop signal. In the initial state, the triggers 148-151 are in the zero state. From the output of the flip-flops 148-151, the prohibitive potentials are given to the inputs of elements 153, 156, 154, and 152, and the enabling potential to the input of element 156. Signals

The survey of the request to RAM is received via bus 36 through the element AND 1b on bus 44.

Block 85 (Fig.7) works as follows.

When entering through the bus 101 applications for recording in RAM 21 trigger

150 through the OR element 159 will be set to the opposite state. There will be no signal at the input of trigger 151, and it will remain in its initial state (the nature of the call is a write to the RAM). Upon receipt of the bus 101 application for reading the trigger 150 and

151 will be installed in single states (character of circulation - read from RAM). The polling signal through the AND elements 156 and 155 sets the trigger 149 and simultaneously, through the OR element 158, the trigger 150 returns to its initial state. The next interrogation signal passes through the AND element 152 to the bus 34, as a signal to the start of the RAM on the bus 103, as a signal to stop the block 89, and at the same time to the input of the trigger 148, setting it in the opposite state. Signals on the bus 36 will not come, so. as ram 21 zan something. The resolving potential from the output of the trigger 148 is fed to the inputs of the elements 153 and 154, as well as to the bus 31, as a control signal.

I

After finishing the work (on writing or reading), the RAM 21 outputs the end-of-work signal, which is supplied via bus 32, through element 153 to bus 102, as a start 2 signal, and through element liDH 157 to the initial setting of the jack. Ers 148-151. Polling bus 36 will start receiving polling signals for RAM as RAM 21 has finished its work. Block 85 is ready to accept a new application.

Fig. 8 shows a functional priority scheme for accessing subchannels to DD 27. To simplify the description of the operation of the priority scheme in each subchannel 7, only individual block elements are available. The scheme checks in subchannels 7 the presence of a request for accessing DD 27 and provides signals, starting up DD 27 to service subchannels 7 in accordance with the established priority: the first serves the first subchannel 7, then the second, etc., the last serviced by subchannel 28 computers. , Following vka can be done

3113

only after the work on the previous application has been completed. In the absence of a quotation from subchannels 7, the polling signal passes to bus 58 (to set the code in block 22) and through the elements OR 5 and AND 17 as the start signal of the CO 27, i.e. in the absence of the subchannel bids, the microprogram will be executed. Subchannel preparation 7 In the initial state, the 13 139 and 105 triggers are in the zero state. From their inverse outputs, the resolving potentials are given to the elements And 15, 143 and 109, and to the elements And 17 141 and 147 - the prohibiting potentials. At the input element And 15 on the bus 50 receives the clock pulses. From the output of element 15, they, as signals from a request to the central office, go through bus 35 to the first subchannel 7. If there is no application, then polling signals pass through element 143 to bus 43 and go to the second subchannel 7, then interrogate the remaining subchannels 7 (provided that there is no quotation). Subchannel 28 is polled last. If there is no application in subchannel 28, then a request polling signal passes through an AND 109 element to the input of an OR 5 element and simultaneously to the bus 58 (to set the start code of the firmware MCU Prepare subchannels 7 when there is no request) . From the output of the element OR 5, the interrogation signal enters through the element AND 17 to the bus 57, as a signal from the start of the control center, and to the input of the trigger 13 to set it to the unit state (the control center is busy). The inhibitory potential from the output of the trigger 13 will block the element 15 for passing the interrogation signals.

At the end of the firmware, the signal of the termination of the control unit operation via the bus 41 transfers the trigger 13 to the initial state (the control unit is free). Element I 15 opens, and from its output, the polling signals for bus 35 reappear. When the signal arrives, the first subchannel 7 sets up a trigger 139 and outputs a inhibitory potential on the And 143 element and allowing it to

ment 141. Interrogation signal of the application for the 55 item OR 4. With the element OR 4

goes through the element And 141 bus 37, the elements OR 5 and AND 17 on the bus 57, as a signal from the start of the control center, and to the input of the trigger 13 to install it in the opposite direction.

the interrogation signal passes through the elements of E 18, as a signal of the launch of the RAM on bus 48, and sets the trigger 24 to a single state, prohibiting the passage

O

0

five

698

32

false state (ZU zanto). The polling signals from the output element And 15 will be blocked until PU 27 finishes executing one of the firmware. The termination signal of the DD on the bus 41, the flip-flop 13 will be set to its initial state (DD freely).

Requests from other subchannels 7 are executed in the same way. If several orders are submitted at once, they will be polled and serviced in order of priority.

Fig. 9 shows a functional 5 priority scheme for accessing subchannels and DD 27 to RAM 21.

The scheme checks the availability of requests for accessing the RAM 21 and provides for issuing start signals for the RAM 21 to service them in accordance with the established priority: first the subchannels of subscribers 7 are served (first first, then second, etc.), then DD 27 and the last one is subchannel 28.

The following procedure can be performed only after the operation of the RAM 21 in the preceding application has been completed.

In the initial state, from the outputs of the flip-flops 24, 149, and 115, the resolving potentials are given to the elements AND 16, 156, and 121, and the inhibiting potentials to the elements And 18, 152, 118, and 130.

5 I

When there is no billing signal, the interrogation of the batch to RAM is not sent to the element OR 4. The input pulses from the output of the element And 16 arrive at the input of the element AND 16 via the bus 50, they, like the signals of the interrogation of the request to the RAM, arrive through the bus 36 of the first subchannel 7. If there is no application, then polling signals pass through AND 156 to width 44 and then through the elements of the last subchannel 7: bus 36, I element 156, bus 44, etc. all subchannels of 7 subscribers are polled successively, DD 27 and subchannel 28. Upon receipt of the signal from the subchannel 7 via bus 101, trigger 149 is set to the opposite state. In this case, the request polling signal passes through the AND element 152 to the bus 34 and enters

0

the interrogation signal passes through the element 18 as the start-up RAM signal on the bus 48, and sets the trigger 24 to one state, prohibiting the interrogation frequency on the bus 36 (the RAM is occupied). After the completion of the operation of the RAM 21, the bus 32 receives a signal. The end of the operation of the RAM, which sets the trigger 24 to its initial state (RAM free).

Applications for RAM 21 from other subchannels 7, 28 and 27 are executed in a similar way. When installing the application in several blocks at the same time, they will be serviced in the order of priority (the first subchannel of the subscriber is served by the first, the second by the second, and so on, the last by the subchannel 28).

In block 2 (FIG. 10), the trigger 160 provides storage for an indication of the mode of receiving information from the computer. The trigger 161 is designed to store the reset unit in its initial state, being fed to the inputs of all the triggers 160-169 and the input register 1 of the exchange on the bus 72.

with the Second of the computer 29, the signal 73 starts the bus which starts the triggers 166 and 167 to the opposite state. From the output of the trigger 166 to the element And 180 na10, the permit potential is given out. From the output of the AND 180 element in the computer 29, signals of unavailability for exchange are output (from the output of the element AND 179, the signals are not detected).

t5 After the removal of readiness, the exchange with computer 29 continues and will be completed after receiving a cres command OR one word of information. From the output of the elements And 179 and 180 in the computer 29 are issued only

sign mode information in the computer. 20 signals ready to exchange or only signals unavailability. The exchange with the computer 29 is carried out in accordance with the organization of the exchange. From the output of the trigger 167, the potential 25 per element I 181 will begin to increase. One clock after receiving the signal, the indication of working with RAM 21 is stored on the trigger 162. The storage of signs by triggers 160-163 is provided for only one exchange with a computer. A trigger 164 provides control of signal generation for accessing RAM 21 and DD 27. Using triggers 165-169, the time diagram of the exchange with computer 29 is performed via inputs 73 and outputs 74. Block 2 ensures the organization of device operation when referring to computer 29 to it. Unit 2 controls the transfer of information words between register 1 and RAM 21. When switching on the supply voltages on bus 100, OR 184 returns the trigger 166 to its original state. From the first output of the trigger 166 input AND gate 179, a second input which receives clock pulses from bus 50. The output of AND gate 179 are output enable signals gateway device to exchange bus 74. Consider the operation unit 2 in the reception mode Infor- .matsii by a computer.

Computer 29 receives the Start Work signal, which sets the trigger 165 to the opposite state (bus 73). At the input of element And 178, the resolving potential starts to come from the output of the trigger 165. A clock pulse passes through the element And 178 and from its output, as a word, the information from the computer 29 begins to arrive. The first word is always the address-command with signs of the exchange mode, initial the address of the reception or issue area and other signs. At the same time, information shift pulses arrive at the bus 73, which passes through the element.

35 And 181 to the input of register 1 and block 3, which controls the correctness of the reception of the address-command. The address command is recorded in the exchange register 1. After this, a signal is received from the computer 29

40 The end of the word on splint 73, which analyzes the state of the elements And 182 and 183.

If the information received is incorrect, then the output potential of the unit 3 is the resolving potential through the bus 76 to the input of the element I 183, the output of which through the bus 74 will give an error signal at the reception. If the information was received correctly, then the resolvable potential from the output of block 3 is fed to the input of the element AND 182. From its output to the computer 29, a signal of correct reception will be given. After receiving the address command, the received signs of the exchange will be recorded in the triggers 160-163 through. 71. If the device receives information from the computer 29, the trigger 160 is set via bus 71

The installation is reset to the inputs of all triggers 160-169 and the input register 1 is exchanged via bus 72.

The second of the computer 29 is fed through the bus 73 signal the beginning of the word, which sets the triggers 166 and 167 to the opposite state. From the output of the trigger 166 to the element I 180, a permitting potential begins to be produced. From the output of the AND 180 element in the computer 29, signals of unavailability for exchange are output (from the output of the element AND 179, the signals are not detected).

After the removal of readiness, the exchange with the computer 29 continues and will be completed after receiving a cres command OR one word of information. From the output of the elements And 179 and 180 in the computer 29 are issued only

The word starts to receive information from the computer 29. The first word of the incoming address is the command with signs of the exchange mode, the starting address of the receiving or issuing area and other signs. At the same time, information shift pulses are received on bus 73, which pass through the element.

And 181 to the input of register 1 and block 3, which controls the correctness of the reception of the address-command. The address command is recorded in the exchange register 1. After this, a signal is received from the computer 29

The end of the word is on the tongue 73, which analyzes the states of the elements And 182 and 183.

If the information received is wrong, then from the output of block 3 the resolving potential is fed via bus 76 to the input of element I 183, from which the output will receive an error signal during reception via bus 74. If the information was received correctly, then the resolvable potential from the output of block 3 is fed to the input of element I 182. From its output to computer 29, a signal of correct reception will be given. After receiving the address command, the received signs of the exchange will be recorded in the triggers 160-163 through. 71. If the device receives information from the computer 29, the trigger 160 is set via bus 71

in a single state. If the device issues information to the computer 29, then the trigger 161 is set to one.

Depending on which unit the computer 29 will work with (with RAM 21 or DD 27), are set respectively to one state or trigger 162 or trigger 163. In the mode of transferring information from computer 29 to RAM 21, the device will be in one state Triggers 160 and 162 are set. At the same time, the signal from the output of the AND element 182 goes through the OR element 187 to the input of the trigger 167 and sets it to the initial state, and to the AND 174 element opened by the resolving potentials from the outputs of the trigger 174 signal arrives on bus 65, as sig al transmission address from register 1 to address counter 12, and through an OR gate 184 - to the input triggers 166 and sets it to the initial state. The resolving potential from its output goes to the input of the element I 179, from the output of which the readiness signals for the exchange begin to appear in the computer 29. The signal from the output of the element And 172 sets the trigger 168, from the output of which the permitting potential will be output to the input of the element And 171 and prohibiting it to the inputs of the elements And 172, 174, 176.

After receiving the ready signal to exchange the computer 29, the first word of information is inserted into the device. Signal Start words on the bus 73 are set to one

At the end of the writing to RAM 21, the bus 78 receives a signal to the end of the work of the RAM, passes through the element OR 185 to the bus 66 as a signal to add

triggers 166 and 167. Through the element 40 laziness +1 in the counter 12 addresses. On and 180, the signals from it will begin to be output; the counter 12 will be set to the following address. The same signal from the bus 78 through the element OR 184 arrives at

exchange on the bus 74. The issuance of readiness signals from the output of the element And 179 will stop, since the output of the trigger 166 and sets

the trigger 166 moves the control 45 to its original state. Through eletruli potentsii.ment And 179 begin to be issued on

The shift pulses from the computer, coming to the bus 74, the readiness signals to the device via the bus 73 are transmitted through the interface to exchange with the computer 29.

ment And 181 bus 72 in the register 1 and in block 3 bus 75.

The first information word enters the register 1 and simultaneously in block 3 to control the received information on the module (for example, module two).

After receiving the information, block 3 imposes a resolving potential on the input element I 183, if the information is

15

n ta wrong. When information is correctly received, block 3 outputs the resolving potential to the input element I 182. After one cycle after reception of the first information word on computer 1, a signal comes from the computer 29 End of word via bus 73, Elements 182 and 183 are analyzed by this signal. We further believe that information is always accepted.

The signal from the output of the element And 182 appears in the computer 29 via the bus 74, as information that the word was received correctly (the signal is true). The same signal passes through the OR element 187 to the input of the trigger 167, sets it to its original state. The signal from the output of the element And 182 passes through the element And 172, open through other inputs by the resolving potentials from the outputs of the flip-flops 162 and 169, and the element OR 186, as a signal to the request for accessing the RAM. Simultaneously with the release of trigger 16, the potential of the nature of the access to RAM 21 (write) is output.

Since the initial address of the zone of RAM 21 was received as part of the address-command, and then rewritten into the counter 12 of the address, and the information word is received on the exchange register 1, when you run the application for accessing the RAM 21, the information from register 1 will be written in RAM 21 at the address set on the 5th one on the counter 12 addresses.

At the end of the writing to RAM 21, the bus 78 receives a signal to the end of the work of the RAM, passes through the element OR 185 to the bus 66 as a signal to add 0

0

0 laziness +1 in the counter 12 addresses. On counter 12, the following address will be set. The same signal from the bus 78 through the element OR 184 arrives at

trigger input 166 and sets

50 Similarly, all other informational words are received from computer 29 and recorded in RAM 21.

After issuing the entire array of information of the computer 29 via bus 73, the exchange termination signal sets the trigger 169. The sign of the end of the exchange with the computer 29 together with the application received via bus 69 is transmitted through the AND 173 element and the bus

39,

in node 22.

When transmitting information to the computer 29, the operation of the RAM 21 and the reading of the informational words are carried out similarly to the recording mode. Only from the exit; the trigger 161 will be issued the disruptive potential of the nature of the circulation (read).

30569838

Nok (at the reception) will be recorded in register 1.

Bus 68 will receive a signal for the termination of work of the CO 27, which passes 5 through the element of the IPI 185 to bus 66, as a signal +1. counter 12 (to set the next address), and via OR 184 to the input of trigger 166. Signals will start

After receiving the address-command start- About readiness from the device to exchange

the new address of RAM 21 will be copied from register 1 to counter 12 by a signal on bus 65. A signal from an output of an AND 182 element through AND 172 and OR 186 will be issued for a call to RAM 21, the Information word will be read from RAM 21 to register 1 The bus 78 will receive a signal for the end of the RAM, which passes through the OR element 185, as a +1 signal to the counter 12 (i.e., will set the next address), and through the AND 184 element to the trigger input 166. From the AND 179 output will begin issue readiness signals to exchange with computer 29.

After reading the word in the computer 29, it issues a signal to the word End, which passes through the elements AND 180, 171, OR 186, as a signal to the application to RAM 21.

The remaining words are read similarly.

After reading the latter, the computer 29 generates a signal for the end of the exchange, which sets the trigger 169,

The mode of operation of block 2 in the case of information with the characteristics of the requisition made in computer 29 differs from the considered modes of receiving and issuing information.

After receiving the address command with the signs of issuing information with signs of a quipped request, the triggers 161 (issue) and 163 (issue request) will be set to one. The signal from the output of the AND element 182 passes through the AND elements 176 and 177 to the bus 67, as per request to the DD. The signal from the output of the element L 176 triggers the trigger 164 to a single state.

HU 27, after receiving the application via bus 67 and signs of exchange over bus 39k, begins to execute the microprogram. Issuance of signs of completed orders (Table 7). After its completion, the word with signs performed in 5

0

five

0

Computer 29.

After issuing the word from the computer 29, the signal comes to the end of the word, which passes through the elements of AND 182, 175 and OR 186 as an application to addressing RAM 21. From RAM 21, a word will be read with signs executed for EOK (for higher) on exchange register 1 .

Bus 78 receives the end of RAM signal (as a start signal from block 2), which is output to bus 86 through the OR element 185, and through the OR element 184 to the input of the trigger 166, to reset it. From the output of the element And 179, signals of readiness of the device to exchange with the computer 29 will begin to arrive. After receiving the word with the signs of the application (to issue) of the computer 29 by the signal of the end of the exchange, sets the trigger 169.

With this, the exchange with the computer 29 in the mode of issuing two words of information with the signs of 5 completed signs ends.

At node 22 (FIG. 11), the decoder 189 provides decryption of the code installed on the counter 190, and issuing pulses to the corresponding output. Counter 190 is used to set a micro-op code. The encoder 191 transitions provide reception and

5 analysis of the signs of operating modes received from the subchannels of 7 subscribers and the subchannel 28 of the computer, and the installation of the 190 micro-code for buses 204 in the counter.

0 The trigger 192-start controls the passage of clock pulses to the decoder 189 and the counter 190, i.e. their start and stop.

The transition trigger 193 controls the operation of the counter clock 190 when the firmware code changes. On buses 199 to 201, respectively, the signals are set to the initial (zero) state, the control potential for

unit 191 transitions and installation in one state of the trigger 193. On the bus 202 the signals of the analysis of the state of the encoder 191 appear; On the tires 203, the potentials governing the operation of the decoder 189 are output. Through the bus 100 when turning on the supply voltages the triggers 192 and 193, and also, the counter 190 is reset, C the outputs of the trigger 192 and 193 are given the inhibitory potentials to the inputs of the elements 194 and 195, i.e. counter 190 with decoder 189 do not work. From the bus 50 to the inputs of the elements And 194 and 195 receives clock pulses.

Node 22 begins to operate when a start signal is received via bus 57, through which trigger 192 is set to one. From its output, the resolving potential will begin to flow to the inputs of the elements And 194 and 195. The clock pulses from the bus 50 through the elements And 195 arrive at the input of the decoders 189 and the counting input of the counter 190. The counter 190 starts counting the pulses, at its outputs 203 they start changing ;: the potentials and the outputs of the decoder 189 successively appear the corresponding signals on the tires 42, 55, 53, 62, 202 and 41.

On bus 39, block 2 receives control potentials and signs from the subchannels of 7 subscribers and subchannel 28, as well as a signal on bus 202 from the outputs of the decoder 189. Under certain conditions, a stop signal 193 is generated, which is issued on bus 201. The trigger 193 is set into the unit state and begins to apply the inhibitory potential to the input of the element AND 195. The clock pulses will cease to arrive at the counting input of the counter 190, but they enter the input of the decoder 189 through the element AND 194.

The encoder 191 on the buses 204 in the counter 190 sets the new firmware code and generates the trigger setup signal 193 to its original state on the bus 199 through the OR 198 element. The counter 190 will continue to work on the new firmware code.

After the execution of a specific firmware from the output of the decoder 189, the bus 41 outputs the signal for the end of operation of the CO 27. This signal is received

In certain blocks of the device and through the element NL1-197, as a signal to stop the operation of block 22, to the input of the trigger 192. Trigger 192 is reset, the inhibit potential of the elements 194 and 195 will start to be given out from its output, Block 22 waits for a new starting signal on bus 57 or bus 61.

Block 23 (Fig. 12) is designed to connect the address counters and registers 7 of the subchannels 28, DD 27 and RAM 21 to magistra 1) ali 26 when transmitting addresses and information. The nature of the trigger 205 controls the operation of block 23 when writing (reading) the address and I1 formation. The trigger 206 of the address-number controls the connection to the highway 26 of the address counters (when writing addresses in RAM) and registers (when writing or reading information). Switches 207 are built on AND, OR elements and provide control signals for connecting the outputs of various registers to the input or output of a numerical register of RAM 21 through line 26, as well as for connecting the outputs of various counters to

the input of the address counter RAM 21 through line 26.

Starting position trigger 205 and address trigger 206

35 address-numbers are set up via bus 100 through the OR element 211, and permitting potentials are outputted to the inputs of the first group, respectively, the switch 207 and the AND element

40 208 and to the input of the elements AND-OR 207 and the element AND 210. From the direct outputs of the flip-flops 205 and 206, the inhibitory potential is output to the element AND 209 and the switch 2072 of the second output 45 and the trigger 206 to the inputs of the switches 207 and 2072.

An example of operation of block 23 when accessing RAM 21 (on writing) of subchannel 28.

After installation, the application to RAM 21 from subchannel 28 over tires 31 and the prohibiting potential (recording) and allowing the 1st potential (arriving from subchannel 28) arrive. From the outputs of the flip-flops 205 and 206, the resolving potentials are output to the AND-OR elements 207, AND 208 and to the switch 207 and the AND element 210, respectively.

A switch potential will be provided to the output elements of the counter 12 subchannel via switch 207 and bus 43, and 28. At the same time, bus 46 will be issued to enable the input address of the RAM 21 address register. When the start signal arrives through bus 48. RAM is written to it, it passes through 3 Lead I 210 to bus 6 (and further to RAM 21) to write the address to 2: 1 RAM. In RAM 21 will be set the address of the cell in which to write the number. The next is a signal to write (or read) a number on bus 49. With this signal, trip 206 is set in the opposite state, and from its direct output, the resolving potential begins to flow to the switch 207. The bus potential 45 will be assigned to the bus potential, which is supplied to the output elements of p € gister 1 (since the application was from subchannel 28). At the same time, a resolution of the thermal to the input elements of the RAM-21 number register will be issued via bus 465-. The signal from the bus 49 is transferred via AND 208 to the bus 46 (and further into RAM 21) as a signal to write information from register 1 to RAM 21. After the RAM 21 has been written, the end of work signal is received, which from the bus 32 through the OR element 211 enters the inputs of the flip-flops 205 and 206 and sets them to the initial state.

21 counters and registers are connected to RAM in the same way.

In the encoder 191, via bus 38, elements OR 219 and I 212, the initial firmware code ZU 27 is set. Preparation of subchannels 7. Tires 39 receive signs of the operating modes of subchannel 28 (respectively Reception - Service, Work with RAM, Read Application and The end of the exchange).

The tires 39 receive signs of the operating modes of subchannel 7 (respectively, the mode of operation of the subchannel and the end of the exchange of the subchannel).

The elements .IL 220 and 221 provide signals on the buses 199 and 201, respectively, of setting to the initial (zero) state and the single state of the transition trigger 193.

On the elements and 213-218 and HE 222 implemented a scheme for the analysis of signs

from subchannel 28 computers and subchannel 7, coming through the bus 39.

Signals are received via bus 202, with the help of which a signal is taken from input to input 39, installation of a triple zero 193 in zero or one state and loading to tires 204 through elements OR 219 and elements 212 of the corresponding

codes executable firmware.

Block 89 (Fig. 14) is designed to control the exchange of information between the RAM 21 of the interface device and the subscriber in accordance with the microprogram executed by node 230. The trigger 223 outputs a gate potential to And 233 and 234 elements when the information words are received and received.

The trigger 224 stores the indication of issuing the address-command. The trigger 225 provides the control potentials of the go-around (uncooperative) subscriber via buses 253 and 254 to block 230. The trigger 226 controls the AND element 210 when recording signs of the computer 29 for microprogram exchange. Preparation of subchannels 7. The trigger 227 stores sign of exchange with the subscriber (reception or issue) for the entire exchange period. The trigger 228 provides the control end potential of the exchange. The trigger 229 controls the element AND 243 when recording the signs of the computer application no. 29 for microprogram exchange. Preparation of subchannels 7. Node 230 generates a sequence of pulses according to a certain microprogram. Counter 231 counts the number of shift pulses and generates an overflow signal. Node 22 control provides

control, for example, modulo two emitted (received) information and produces signals true or

Mistake. I

Block 89 contains the following tires

transmission of control signals: bus 30 - control and information exchange signals between block 89

and subscriber, subscriber readiness, subscriber capacity, start of work, start of word, end of word, shifts, end of exchange, true, information from the subscriber,

Information to the subscriber, Error, bus 37 for transmitting the signal - stopping operation of node 230, bus 38 for transmitting clock pulses of the operating frequency of sub-channel 7, bus 39 for transmitting control

43130

Potential operation of the subchannel and the end of the exchange of the subchannel, 1: 1in 40 transmissions of the potential of the connection podknalll 7 to DD 27, bus 40 and 40 reception n) iznakov computer 29 on reception and higher, bus 40j and 40 vy / (1CH Signals of the source and the sign of the application, bus 42, receiving signals, recording, charging, computer 29, for exchanging, bus 90, receiving a signal, Application for accessing a central control, bus 91, receiving signal, starting G, bus 92 , the bus 93 setting the code of the starting address, the bus 94 receiving the signal overflow word counter, bus 97 receiving information information, bus 98 information, bus 99 shift pulses, bus 110 for setting the initial signal when power supply is turned on, bus 101 for signal, Application for accessing RAM, bus 102 for receiving signal Start 2, bus 103 for receiving signal Stopping a node, pulse transmission bus 248 — from the output of node 230, respectively Starting up, Starting a word, End of a word, Exchange end, Shifts, Application for accessing RAM, +1 into the counter, Setting the starting address, overloading bus 2L9 counter 231 shifts, signal transmission bus 250 setting to the initial state; Transmission bus 251 sign for address-command, bus 252 for transmitting a call-to-AC attribute in receive mode, bus 253 and 254 for transmitting signs of readiness and subscriber unavailability for exchange, bus 255 and 256 for transmission Signs True and Error.

When the supply voltages are turned on, the block 89 is reset to the initial state by a signal received via the bus 100. The algorithm of the control block 89, the exchange, is shown in Table 9.

In node 230 (FIG. 15), trigger trigger 260 provides control for pro44

O

15

0

five

by passing the clock pulses along the bus 38 through the i 263 and 262 elements to the counter 258 and the decoder 257. The transition trigger 261 blocks the passage of the clock pulses through the AND 263 element to the input of the counter 258 if the microprogram code needs to be changed.

In the initial state, the trigger 260 outputs a inhibitory potential to the inputs of the And 262 and 263 elements.

The trigger 261 gives the permitting potential at the input of the element And 263 and prohibiting the bus 268 to the encoder 259 transitions.

The start-up of node 230 is effected by a Start 2 (RAM end) signal via bus 102 or a Start 1 (End of Operation 27 signal) by. bus 91 when arriving at the OR 265 element. The operation of the node 230 is accomplished by setting the application signals when the RAM 21 is accessed via the bus 103 or when the DD 27 is accessed via the bus 37 through the OR element 264. The algorithm of operation of block 230 is described in tab.9.

In the encoder 259 (Fig. 16), And 272 elements are written to the firmware code (after analyzing the characteristics) via buses 270 to the counter 258. The connection of the elec. And 272 to the counter 258 is carried out by the potential on the bus 268. 35 Through the elements OR 282 and 283, the signals of the installation are output to the single and zero states of the trigger 261, respectively.

On the bus 271, the signs analysis elements 273-280 receive impulses from the output of the decoder 257 and control potentials via the tires 251 (indication of address-command), 252 (indication of address to the central control unit in receive mode), 249 (overrun of shift counter 231) , 253 and 254 (signs of subscriber readiness and occupation), 255 and 256 (True signals, Error).

thirty

40

45

45

1305698

A1

Turn on the supply voltage. Initialization of the device

46 table

/ Analysis of the exchange of A5 with a computer 29

To DD 27

Analysis of the wok to RAM 21 or DD 27

Ram 21

Analysis of the availability of the application to the CO 27 (Fig. 8)

there is

A3 Appeal to DD 27 (Table 3)

Not

Not

Analysis of the availability of the stock to RAM 21 (.1) and 9)

Pc .7

. V

Pc 7

em

A4

Preparation of subchannels 7 (table 4)

A9

Start subchannels 7 (table 5)

All

Formation of signs performed by the request (Table 6)

A10 Work subchannel 7p (Table 8)

Applications to RAM 21 and DD 27

PC 28

12

Formation of signs performed by the request (Table 7)

From DD 27

A8

From pc 7

there is

From pc 28

Appeal to the RAM 21 (table 2)

DD 27

PC

one-

PC 28

to blocks A10 - A10 „

To A4 A4, AI, A12 blocks

B1

The trigger 24 is in the zero state (RAM is free). The inverting potential at the inputs of the elements U and I 18 is output from its inverse output. The prohibitive potential at the input of the element 19 enters the direct output of the trigger 24. The clock pulses from the generator 14 pass through the element 16 as signals to the RAM bus 36.

B6

Block 23 connects via bus 45 to the trunk the address register of that subchannel 7, which generated the start signal, and the address register of the RAM and supplies the .46 load to the RAM 21 with the address write signal. The address of the cell is recorded in RAM 21. Simultaneously with the start signal, control signals of the nature of the circulation (write or read) and the potential of the application are made on the bus 31.

B7

After two clocks at the output of the delay element 25, a delayed start signal appears, which, through the element 19, enters via the bus 49 to the input of the unit 23 for writing or reading the information word from the RAM.

table 2

To block B6

From block B5

B8

Block 23, after analyzing the control signal of the application to RAM 21 and analyzing the nature of the circulation (recording or reading), connects via bus 45 to highway 26 the outputs of RAM 21 and the register inputs of the corresponding subchannel 7 or DD 27 (in read mode) or connects inputs RAM 21 and the register outputs of the corresponding subchannel or DD 27 (in the recording mode of the information word). The start signal of the RAM 21 to write (read) the information word enters from block 23 into the RAM 21 via bus 46. The information word is written (read) into the RAM (from RAM) at the address set on the RAM address register.

B9

Upon completion of the write (read), the RAM 21 issues a signal. The end of the RAM operation via the bus 32. This signal sets the RAM access unit that generated the RAM start signal, the block 23 and the trigger 24 to reset.

The trigger 24 begins to issue a permitting potential to the inputs of elements AND 16 and 18 and an input element forbidding elements B10 and 19. With the output of element I 16, the interrogation signals for RAM will begin to flow through bus 36 to RAM. RAM is prepared for new access.

B1 Trigger 13 is in the zero state (DD 27 freely) The resolution potential at the inputs of the AND 15 and 17 elements is output from its output. Through the AND 15 element, the polling signals from the search module to the CU pass through bus 35. Block 22 does not work.

Interrogation signals for remote control 27 sequentially interrogate blocks 84 (input 35, output 43 buses), then block 8. If there is no intermittent request, the interrogation signal for thermal control is received from B2 of block 8 via bus 58 as the start signal of central control unit 27. The same The signal at node 22 sets the code for the start of the firmware. Preparation of subchannels 7 in the absence of a bill. The start signal of the DD 27 passes through the elements OR 5, AND 17 to the inputs of the block 22 and the trigger 13.

GZ

Upon detection of a request to DD 27 in any of the subchannels 7 or block 8, a trigger signal is issued from DD 27, which arrives at the OR 5 element on buses 37 and 59. Further work of DD 27 is the same when running the same firmware for subchannels 7 and 28.

Continuation of table 2

To block EY

From block B9

Table 3

51

B4

The start signal of the CO 27 via the bus 57 from the output of the element OR 5 through the element And 17, opened by the resolving potential, enters the inputs of the trigger 13 and the input of the node 22.

B5

The trigger 13 is set to one state (DD 27 is occupied), at the inputs of the elements 15 and 17, the inhibitory potential.

B6

After receipt of the start signal, node 22 analyzes the signs coming in to the women 39 and, in accordance with them, sets the start code of one of the microprograms and generates a series of pulses.

B 7

After the firmware has been executed, the node 22 issues a bus-41 termination signal for the DD 27, which sets the block 84, which triggered the start signal, and the trigger 13 to the initial state. The trigger 13 begins to issue an enable potential to the inputs of the AND 15 and 17 elements. And 15 again, the polling signals of the request to the CO will begin to arrive. DD 27 is prepared for new circulation.

1305698,

52 Continued table. 3

To block B6

From block B5

Table 4

53

1305698

56

Signs from the output of the node 22 through 42 rewrite the signs of the computer bill (at the reception) from register 6 to subchannels 7. The signs of the check are entered into subchannels 7 via tires 40.

B 7

The signal from the output of the node 22 on the bus 53 is set on the counter 11 the address of the second cell of the area of the RAM 21 (computer application for issue)

54 Continuation of table 4

To block B8

From block B7

From block B5

Table 6

57

1305698

GZ

Computer 29 to receive) if information from subscriber 30 was received by subchannel 7, or the address of the second cell of this zone is set (in which the word with signs of the computer 29 for issuance is stored), if information was sent to subscriber 7,

B4

Bus 62 establishes a request for RAM at node 9. Operation stops at node 22.

B5

Accessing the RAM 21 via the bus 51 to read the word from the cell area of the RAM 21 whose address is set on the counter 11, Reading the word with signs of the computer 29 to the register 6 through the trunk 26. The end of the RAM 21. Setting the node 9 via bus 32. Starting node 32 via bus 61,

58 Continuation of table 6

To block B6

From block B5

To block B11

From block 10

59

1303698

one

60

Continuation of table 6

To block & 16

From block B15

61

B4

Bus 62 establishes a request for RAM in node 9. Operation of node 22 stops.

B5

Appeal to RAM 21 via bus 51 to read a word from the third cell of RAM zone 21, whose address is set on counter 11. Read a word with signs of filling (reception) to register 6 through line 26. In the case where subchannels 7 did not complete exchanges with subscribers, in this cell there will be a zero word, i.e. with no signs performed for the wok (at the reception). The end of the RAM 21. Setting the initial state of node 9 via bus 32. Starting node 22 via bus 61.

B10

Appeal to the RAM 21 on the bus 51 to write a word into a cell whose address is set on the counter 11, i.e. in the third cell of the RAM zone 21. Record of the contents of register 6, i.e. zero word, through the trunk 26 in the RAM 21. The end of the work of the RAM 21. Setting the node 9 to its initial state via the bus 32. Starting the node 22 via the bus 61.

From BID block

1305698

.L

62 Continuation of table 7

To block B6

From block B5

To block B11

B15

Appeal to the RAM 21 on the bus 51 to write the word in the cell, the address of which is set on the counter 12 of the subchannel 28. On the counter 12 is the first address. Writing the word with the signs of fulfilling the request (for issue) from register 6 through line 26 to the first cell of the RAM zone 21.,. Graduated

operation of RAM 21, resetting node 9 via bus 32, adding 1 in counter 12, subchannel 28. Starting node 22 via bus 61.

B16

From the output of node 22 through the pin 55, the program readiness register 6 is set to zero.

h:

B17

From the output of the node 22, the bus 62 is applied to the RAM in the node 9. The operation of the node 22 stops.

B18

Appeal to the RAM 21 on the bus 51 to write the words in a cell whose address is set on the counter P, i.e. into the fourth cell of the RAM zone 21. Writing the contents of register 6 (zero word) through line 25 to RAM 21. Shutdown of the operation of the AZS 21. Initialization of node 9 via bus 32. Starting node 22 via bus 61.

From block B18

To block B15

From block B14

To block B19

65

1305698

J

To Block B23 From Block 22

B23

End of microprogram

66 Continuation of table 7

Table

Analysis of operating modes and directions of exchange

Issuance of information to the subscriber 30

Reception of information from the subscriber 30

B5

Appeal to the RAM 21, One word is read from the cell area of the RAM 21 | whose address is set on the counter of the subchannel address 7, to the register 88 of subchannel 7.

B6

End of RAM operation. +1 is added to the subchannel 7 address and word counters.

To block B7

From block B6

B7

Entering one information word from the subchannel 7 exchange register to the subscriber 30

pet (B8 Analysis of the end of the exchange to the block | B4,

B11

Reception from subscriber 30 of one information word to subchannel 7 exchange register

B12

Appeal to the RAM 21. One word is written into the cell of the zone of RAM 21, whose address is set on the counter of the subchannel 7 address, from the subchannel 7 register.

B13

The end of the operation of the RAM 21. It is added to the counters of the address and words of the subchannel 7.

B14 Analysis of the end of the exchange / B9

Application to DD 27 for the execution of the firmware

To block 4 Analysis of the end of the subchannel work No

XX V-f.

-J

I. I..I .. ... f- - - .- .- ..

I B15 End of subchannel operation 7.

To block 511,

From block B4

To bl

XX V-f.

-J

69

1305698

From block B25

B1

B2

Subchannel 7 subscriber start

one

Starting node 230 via bus 91 from node 22 (after running the microprogram Starting the subchannel)

GZ

The signal from the output of the node 230 on the bus 248. Analysis of the presence of a signal of readiness for exchange from the subscriber arriving on the bus 30. Installation in 1 trigger 261 (Fig.15) on the bus 269.

No readiness

B4

Waiting mode signal alert from the subscriber.

B6

The signal from the output of the node block 230 bus 248. Issuance of

Signal Subscriber Getting Started Through Element And 236 And

bus 30,

Setting trigger 224 (write to the command address entry)

From B19

Analysis of the issuance of the address-command and the mode of work with the subscriber (reception or delivery)

Enter the address-command "or mode to block B8

From block B7

B8

Appeal to the RAM 21 at the address of the counter 86 to read the address-command in the register 88. Issuance of the application on the bus 101. Stop the node 230 on the bus 103.

B9

Reading the address of the command (or word of information) from the RAM 21 to the register 88. The end of the RAM 21. By the signal of the end of the RAM 21 start node 230 bus 102.

B26

Formation of the next clock cycle node 230,

70 Table 9

Start subchannel from CO 27

Have

No address-command and reception mode to L block B26

From block B7

B10

The output of the node 230 via bus 2482-Issuance of a signal The beginning of a word to the subscriber through an AND 237 element via the bus 30. Setting the trigger 223 into one state (preparing the elements AND 233,

And 234 to issue or receive information). Installation in 1 trigger 261 (Fig.15).

From block B13

B11

In node 230 via bus 251. Analysis of the issuance of the address-command and the mode of operation with the subscriber (reception or service).

Issuing an address-command or mode of issuing information

B12

Inserting one shift pulse into counter 231 at input 248, and into register 88 via bus 99. Inserting one bit of information from register 88 via bus 97 into a subscriber through element 233 and bus 30 ,.

To block B13

From block B12

B27

B13

Node 230 bus 249: analysis of overflow of counter 231 shifts.

From the output of the node 230 via bus 248 ,,: set to О of the trigger 261, outputting the signal End of the word to the output 30 to the subscriber. Setting to the initial state through the OR element 245 triggers 223 and 224. TG- No address-commands and reception

To block B27

From block B11

Insertion of one pulse of information shift on the bus 2485 to the counter 231, to the register 88 via the bus 99 through the I element 238, via the bus 30 to the subscriber. Reception of one bit of information from the subscriber on the bus 30 through the element And 234 and transmission to the register 88 on the bus 98.

To block B11 No overflow

There is an overflow

73

1305698

..

Node 230 on buses 255 and 256: analysis of the presence of a signal Correct from the subscriber (checking the status of node 232 of the control module, which must be received through several; on the bus 30-T1.

74 Continuation of table 9

To block B16 From block 15

There is a signal right

B16

In node 230; analysis of the mode of operation and issuance of the address-command /

Extradition

From block 529

To block 30 From block 15 There is a signal Error

BSO

Subscriber malfunction Subscriber stop working

Reception

To block B28

B17

At node 230, bus 94: analysis of the overflow of the counter 87 words of subchannel 7.

There is

to block 20

B18

From the output of the node 230 via bus 248: adding +1 to the counter 86 addresses and 87 words on the bus 92. Installation in 1 trigger 261.

B19

From the output of the decoder 257 via bus 271: setting the firmware code to go to the block B7 of the present algorithm. Installation in About Trigger 261

To block B7

B2

From the output of node 230 via bus 248 .: installation of the application to DD 27 through element I 293, element ISH 247 via bus 90 in block 84 of subchannel 7. Stop of operation of node 230 via bus. 37. Execution of the target point 27 of the microprogram. Formation of signs of fulfilled requests.

From block B19

B25

Analysis of the presence of a start signal from the CO 27 on the bus 42

there is

CHK block B1

From the output of the node 230 via the bus, send a request for accessing the RAM 21 via the bus 101. Stop the operation of the node 230 via the bus 103. The mode of recording information in the RAM 21 at the address set on the address counter 86.

B29

Writing a word of information from register 88 into RAM 21, End of operation of RAM 21. Starting node 230 via bus 102.

To block 517 1

To block B25

From block B24

Not

B31

R

End of subchannel 7

From block B16

To block 29

From block B28

59

-.,

77P,

t

A5

Pi

Fi.5

fut.6

Ya73

fPu9.e

Phage. 9

Tt

FIG. YU

50

57

61

FIG. eleven

105

l g

3 / l

X ... X.

3f,

J /.

/ n

-

-

-

2/7

h: i

Z / 77

g

-h--

V5

. G2

/ Xo

Schi B C 0 Record

2P

23

100

.32 3f 5

Record is clean Wli

45im

511

5r / i

Jan.

46,

five

Count

VJy

// 52/3 /

Y5g / U

1-vj y

V5J7

53t /

: 45vy

t

j

A

Phie.1

31 99

34

Sfi

YU

cs,

270iTiOtziOn-, nOn

255

,,,,

TTt ti

3

 r i. 7 r

281,

Z8Zz

W9

2vg

zn

t

28,

Editor V.Danko

Compiled by V. Vertlib

Tehred A. Kravchuk Proofreader C, Shekmar

Order 1453/47 Circulation 673 Subscription

VNIIPI State Committee on the USSR

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab ,, d.4 / 5

Production and printing company, Uzhgorod, Projecto st., 4

fSi 2lfS tS3-ZSS

Z7}

isi

ff9

Zlh

f% J

278

271.

Claims (3)

1. A DEVICE FOR COMMUNICATING A COMPUTER WITH SUBSCRIBERS, comprising a computer subchannel consisting of an address counter, an exchange register, a module control unit and a computer exchange control microprogram unit, a memory unit, a pulse generator, and η subscriber units, each of which consists of an address counter , a word counter, an exchange register, and a microprogram exchange control unit with a subscriber, the command input and group of outputs of which are the corresponding input and output of the device for connecting information and control outputs and the corresponding subscriber, and in each subscriber’s subchannel, the first information output and information input of the exchange register, the output of the word counter and the counting inputs of the address counter and word counter are connected respectively to the second information input and output, the first input of the condition and the third output of the microprogram exchange control unit with the subscriber, in the computer subchannel, the output of the address counter is connected via the trunk to the address input of the memory unit, and the first information input is connected to the first output of the computer subchannel exchange register, the second the output of which through the highway is connected to the information input of the memory unit, and the third output is to the enable input of the control unit modulo, the output is connected to the first input of the conditions of the microprogram control unit for computer exchange, the second input of conditions and the first - the third outputs of which are connected respectively to the fourth the output and control input of the exchange register, the recording input and the counting input of the counter of the computer subchannel address, and the clock input - to the output of the pulse generator, characterized in that, in order to expand the class of of the device’s tasks, it includes a central control unit, a frequency divider, a trunk switching unit, a memory busy trigger, three AND elements, an OR element and a delay element, and a call block to the central control unit in each subscriber’s channel and computer subchannel and a memory access node, and in the computer subchannel, the first information input and the fourth output of the exchange register are respectively the input and output of the device for connecting to the information output and the computer input, the second information inputs of the address counter and the register of the exchange of the subchannel of the computer and the information input of the control unit modulo are connected through the highway with the information output of the memory unit, the clock input of the pulse generator connected to the output SU, „. 1305698 owls, to the clock input of the central control unit and through the divider cha-. frequencies - to the clock inputs of the microprogram exchange control blocks with the subscriber, the first condition inputs of which are connected to the group of control outputs of the central control unit, in the computer subchannel the third condition input and the fourth output of the microprogram exchange control unit with the computer are respectively the input and output of the device for connecting to the control the output and input of the computer, and the fifth, sixth and seventh outputs, respectively, with the synchronizing input of the control unit modulo, with the request input of the memory access unit and the unit rotation to the central control unit, the start and request outputs of which are connected respectively to the fourth and fifth inputs of the conditions of the microprogram exchange control unit with the computer, the sixth condition input connected to the start output of the memory access node, the polling input of which is connected to the request polling output to the memory of the central unit control, the request for polling output to the central control unit of which is connected to the polling input of the access block to the central control unit of the first subchannel of the subscriber, the polling output of the the extension to the central control unit of the i-ro subscriber subchannel (ί = Ϊ, η - 1) is connected to the polling input of the access block to the central control unit of the i + 1th subchannel of the subscriber, the output of the polling unit of the call to the central control unit of the ηth subscriber connected to the polling input of the access block to the central control unit of the computer subchannel, the polling and start outputs of which are connected respectively to the first and second start inputs of the central control unit, the end of operation of which is connected to the reset inputs of the access blocks to the bl to the central control of the computer subchannel and subscriber subchannels, the first start outputs of the access blocks to the central control unit of the subscriber subchannels are connected to the start input group of the central control unit, the mode input group of which is connected to the eighth output of the microprogram exchange control unit with the computer with the fourth outputs of the microprogram exchange control unit with a subscriber whose fifth outputs and second inputs of conditions are connected to the group of inputs / outputs of signs of claims of the central control unit, hell The solid output and the command input-output of which are connected respectively through the highway with the address input and the information input of the output of the memory block that controls the input of the trunk switching unit connected to the first output, the second output of which is connected via the highway with the inputs for allowing the counters of the address and exchange registers of the sub-channel to be connected to the highway The computer and the subscriber’s subscriber and the permission enable input to the main line of the central control unit, the group of inputs of the OR element is connected to the memory start outputs of the block central control and memory access sub-channels and computer sub-channels, the reset inputs of which are connected to the output of the end of the cycle of the memory block, the reset input of the memory busy trigger and the first control input of the trunk switching unit, the second control input and synchronization input of which are connected respectively to the outputs of the first and the second AND elements, the first inputs of which are connected respectively with the inverse and direct outputs of the memory busy trigger, and the second inputs are respectively the outputs of the OR element and ele entent of the delay, the input connected to the output of the first AND element and the installation input of the memory busy trigger, the inverse output of which is connected to the first input of the third AND element, the second input and output connected respectively to the output of the pulse generator and the polling input of the memory access node of the subscriber's first subchannel, output the polling of the access node to the memory of the i-ro subscriber subchannel is connected to the input of the poll of the access node to the memory of the i + 1st subchannel of the subscriber; m of polling applications to the memory of the central control unit, the outputs of the access mode of the central control unit and the access nodes to the -memory of the subscriber’s subchannels and the computer subchannel are connected to the group of information inputs of the main switching block and the memory block mode input, in each subscriber’s channel the first and second start outputs and the output of the request sign of the access block to the central control unit and the start and stop outputs of the memory access unit are connected respectively to the third, fourth, fifth and sixth inputs of the conditions of the mic unit program control exchange with the subscriber, the sixth, seventh and eighth outputs of which are connected respectively to the inputs of the requests of the access block to the central control unit and the memory access node and to the clock input of the exchange register, the second and third outputs of which are connected respectively to the information input of the word counter and the first the information input of the address counter, the output and the second information input of which are connected via the trunk, respectively. indirectly with the address input and information output of the memory block, the information input and output of which is connected to the input-output of the exchange registers of subchannels of subscribers, the central control unit comprising a memory access node, an address counter, a program readiness register, a busy trigger, two AND elements, an element OR and a microprogram control unit, the first to fourth condition inputs and a group of condition inputs of the microprogram control unit respectively connected to the outputs of the first AND element, the stop output and the lane by the output output of the start of the memory access unit, the first input of the start of the central control unit and the group of operational inputs of the central control unit, the first, second and third outputs of the firmware control unit are connected respectively to the control input of the program ready register, the counting input of the address counter, the request input of the access unit to memory and a group of control outputs of the central control unit, and the clock input and the fourth output, respectively, with the clock input of the central control unit and the first input of the second AND element and with the output of the end of the central control unit and the reset input of the busy trigger, the installation input and output of the first AND element connected to the output and the first input, the second input of which is connected to the output of the OR element, the group of inputs of which is connected to the first and second inputs the start of the central control unit and the group of start inputs, the second input and the output of the second element And are connected respectively to the output of the busy trigger and the polling output of the central control unit, the first and second information the input-outputs of the program readiness register are connected respectively to the command input-output of the central control unit and the input-output of the signs of requests of the central control unit, allowing input - with the permission input for connecting to the main line of the central control unit and the enabling input of the address counter, the output of which is an address output central control unit, second start output, mode output, reset input, polling input and output of the memory access node are connected respectively to the memory start outputs, ma memory access input and the reset input and the output polling requests to the central control unit memory. 2. The device according to claim 1, characterized in that the memory access node contains four triggers, five AND elements, two OR elements and a switching element, wherein the installation input of the first trigger is connected to the output of the first AND element and the outputs of the memory start and stop the node, and the output is with the first inputs of the second and third AND elements, the output and the second input of the second AND element are connected respectively to the first input of the first OR element and the node start output and the node reset input, the output of the fourth AND element is connected to the installation input of the second trigger and the first input of the second OR element, the output connected to the reset input of the third trigger, and the second input - with the output of the first OR element and the reset inputs of the first, fourth and second triggers, the direct and inverse outputs of the second trigger are connected respectively to the first inputs of the first and fifth AND elements, the second the inputs of which are connected to the input of the node polling, the output of the fourth trigger is connected to the second input of the third element And, the output of which and the output of the first trigger form the output of the node inversion mode, the first and second inputs are even The elements of the And element are connected respectively with the output of the fifth And element and the polling output of the node and with the output of the third trigger, the installation inputs of the third and fourth triggers are connected respectively to the first and second outputs of the switching element, the first and second inputs of which form the input of the request to the node memory, the second input of the first OR element is the input of the initial installation of the node. 3. The device according to claim 1, with the proviso that the access block to the central control unit contains three triggers, four AND elements and three OR elements, the reset inputs of the first and third triggers being connected respectively with the outputs of the first or third elements OR, the first inputs of which are connected to the input of the initial installation of the unit, the direct output of the second trigger is connected with the first input of the first element And, the output connected to the first output of the start of the unit and the installation input of the first trigger, the output of which is connected to out block request and the first input of the second AND element, the second input connected to the block reset input, and the output to the second inputs of the first and second OR elements and the second block start output, the second input of the first AND element is connected to the polling input of the block and the first input of the third element And, the second input of the second trigger connected to the inverse output, and the output - to the block polling output and the first input of the fourth AND element, the output of which is connected to the installation input of the second trigger and the second input of the third OR element, and the second input - output of the third flip-flop input coupled to the mounting block input request.