SU741259A1 - Interface - Google Patents

Description

The invention relates to computing and can be used, for example, to interface digital computers with stochastic integrators in the construction of hybrid computing systems.

There are known interfacing devices comprising a block of buffer registers connected by inputs to the corresponding inputs of the device, a polling distributor, a control unit, a synchronization unit and an address generation unit, and performing functions of controlling the organization of the exchange between objects and the digital computer 1.

The disadvantage of these devices is limited functionality and low speed, since the object is selected sequentially regardless of its state.

The closest to the technical essence of the invention is the interface device / containing a buffer register, an address counter, an address decoder, an operation code register, a characteristic register, a characteristic decoder, a data counter, a reversing converter and a control unit, and performing the functions of a DVR with digital integrator. In the device, input of the initial data in each functional direction is preceded by the transfer of the control word, which the Control command is executed by, and then the information is transmitted (execution to the Write commands). The control word contains the sign code transmitted

10 information, the code of the address command for entering a number, the code of the setting command of the memory device, as well as the start or reset commands. When executing a command

15

Write down

A single information word or group of words is transmitted to the integrator in the functional direction specified by

Control

command execution

20

The output of the results of solving the problem is also performed by transmitting the control word from the digital computer indicating the functional address of the read information and direct

25 transferring the solution results from the integrator to the digital computer when executing the Read 2 command.

The disadvantages of this device are limited functional

30 possibilities and low speed.

conditional by the fact that it doesn’t allow op-ganisoat e; -.-; .., to get information from a digital computer without.; i y: p; | which is not enough for kc.kkogo o.ch.ionalnyh directing, can not information in the digital computer without a command of issuance from it, does not allow to form a state code of integrators, which crashes the intermediate or final stage of solving the problem. And also does not provide the Forms of the information about ;;;. Contents of the intermediate or final results of solving the problem for success in the digital computer.

The aim of the invention is to improve the speed of the device.

The goal is achieved in that a device for interfacing containing a buffer register and a control unit connected by first inputs and outputs, respectively, to the information input and device outputs, a status register connected by inputs to the corresponding inputs from the group of state object inputs of the device , the second output of the control unit is connected to the launch output of the device, a memory is entered, two delay elements, a priority node and a group of blanking elements, the first inputs of the blanking elements and the group are connected to corresponding indicator 3xo, devices1., the second inputs - with the corresponding. the outputs of the priority node and the outputs from the group of address outputs of the device, the control input — with the third output of the control unit Lenin and the control input of the buffer register; The priority node, the control output connection with the second control unit input, and the second information output; device output, the register output is 1 and connected to the memory information input, the output of which is It is controlled by the third input of the buffer register, and the control input through the first and second delay elements, respectively, to the control inputs of the status register and the device and the third input of the control unit.

The drawing shows the block diagram of the device.

The device circuit contains a buffer register 1, a priority node 2, a group of 3 elements and a gaiteni unit constituting the cyclic exchange organization block 4, a memory 5, a state register 6, the first 7 and the second 8 delay elements 6 constituting the instruction generation unit 9, and a control unit 10, a specialized device 11, including stochastic integrators 12 and a control unit 13, and an information highway 14 for communication with a digital computer.

The cyclic exchange unit 4, when receiving information from the DI.M., receives an address word indicating the functional direction and order of the source information in the information packet transmitted to the associated device, distributing information in accordance with the address and signal slots contained in the address word, as well as receiving and storing codes, modes of operation of the corresponding device.

When the intermediate or final results of the problem are solved on the digital computer, unit 4 receives from the block 9 integrator status codes and address signals that determine the functional indication and order of the information in the information package, and also connects the integrators according to the address word to the information highway for issuing the result of solving the problem on a digital computer. The control unit 10 is designed to control the exchange of information between the digital computer, unit 4 and the associated device during input and output of information.

The block 9 of the forging instruction on the positional state signal signals coming from the associated device generates a state code and an address word that indicates which floor it is; intermediate or final information will be issued to the digital computer, which the functional sense in it is concluded and in what order it is necessary to issue it.

In register 1, when receiving information from the digital computer, the address word and the mode code of the associated device are entered. In the address word, each integrator 12 is allocated an address bit, the presence of a unit in which indicates that with this exchange information will be entered into the appropriate integrator. The address number of the address bit in register 1 determines the order of the information being entered into the selected integrator 12. The priority node 2 selects the address integrator, 7 for the 12th, single. in the address register register I which has the highest priority. At the same time, the address signals arrive at elements 3 AND groups through which, after entering information .vj, the selected integrator suppresses (resets) the address bit of register 1 that was selected by the node. 2. At the same time, at the output of node 2, the address of the following functional direction is chosen.

When issuing the result of the decision on the digital computer, the address 1 is entered into register 1

word and integrator status code 12. In this case, the address word indicates from which integrators and in what sequence information will be output to the digital computer.

The device works as follows.

When receiving information from the digital computer, the first information package containing the address word and the mode code is entered into register 1 and fed to node 2 to select the address of that integrator 12, whose address unit in the address word has the highest priority, and on information highway 14 from the DVR There is information that you need to bring B selected integrator. After entering the information, this integrator 12 generates a signal of awareness, which is fed to the elements of 3 AND groups. The signal from block 10 is used to extinguish (reset) the address bit corresponding to the given integrator. Node 2 selects the next bit of the address word stored in register 1 in which the unit is written and connects the address signal to the next integrator

Similarly, information is recorded in other integrators, the units in whose address bits have been entered in register 1 when exchanged on a given cycle. .1 After entering information into all integrators marked with units in the address word received from the digital computer, node 2 generates a control signal that enters block 10 and notifies that information has been entered. Block 10, in turn, launches integrators to perform the main operation. The mode code from register 1 enters the block. 13 to indicate the type of protection and the mode of its solution.

The output on the digital computer of intermediate or final results of the task is carried out by the initiative of device 11. At the same time, the integrators form positional signals that are entered in register 6. The contents of register b are the address of memory cell 5, where the instruction is stored. during the recording of the state signals into register b from the output of the first element 7, a memory trigger signal is generated. After the time required to read the information from the memory, the second delay element 8 generates a signal arriving at block 10 and notifying it of the completion of instruction generation. This instruction contains device code 11, as well as an address word indicating from which integrators 12 and in what sequence the output will be made.

accumulated information for this exchange with digital computers.

In this case, the first word on the digital computer transfers the contents of register 1, and then, in accordance with the state of 2 bits, the address word is organized in turn to issue information from integrators 12. Moreover, the order of information output from integrators is determined by their location

... address bits in the address word of the register 1.

After issuing information from the next integrator, its address bit is cleared in the address word of register 1, node 2 selects

5, the next integrator and block 10 allow the output of information to the digital computer from the newly selected integrator.

Thus, the device allows you to connect

0 integrators solving one common

task, and organize the exchange of information in such a way that all information entered from a digital computer or output to a digital computer is accompanied by only one

5 with the service word, and this reduces the time of information exchange between digital computers with interfacing devices.

The device also allows cyclical exchange of information in the process of solving a problem with the output on the digital computer not only of intermediate or final results of solutions, but also state codes indicating how this solution passed,

G in turn expands the functionality of the device.

Claims (1)

1. USSR author's certificate according to application number 2339617, cl. G 06 F 3/0 2, USSR Author's Certificate 519704, cl. G 06 F s / 04, 1974 (prototype).