SU444184A1 - Information processing device - Google Patents

Description

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The invention relates to computer technology and can be used in universal and specialized computer computing (CMV),;

Modern digital computers and systems consist of a large number of asynchronously operating devices, processing, storing or transmitting information, General control. Such a system is carried out by a processing device; a program operating according to the program; In order to obtain an optimal ratio between performance and cost for small and medium-sized systems, it is preferable to use processing resources of the It.e. registers of the adder, etc.) to perform certain functions of the device TV, transmit data (input-output devices). The specificity of the organization of the interaction between the processing devices and the automatic

The hardware of the I / O devices (hereinafter referred to as I / O Units) is that the processing device and I / O units are pa. asynchronously in relation to each other. In addition, in most processing devices of modern computers, microprogram control is used, and in one cycle of operation of the device, the execution of the current microcommand and sampling from the memory of the next microcommand are combined. Further more complex interaction takes place in the case of the presence of registers and triggers in the processing device, the state of which changes each cycle of operation of such a device and can be interrogated by the microprogram control unit to form the address of the next microcommand.

A known system that includes autonomous I / O devices (blocks), each of which can be either informed or stored with a storage device (RAM) through a central processing device. Each of the I / O blocks exposes one or more requests with different priority, which are analyzed by the special equipment of the processing device, and the equipment carries out the determination of the most priority request and the determination of the moment of the beginning of the processing of such a priority. tstv1Sh allocation request from a processing device address formation is carried out microinstructions Correspondingly vuyuschey dedicated request, receiving and blocking into register Inforga FIPA microinstructions from the memory address of the micro instruction ,, which was Form van in the previous cycle of operation. In this case, the microinstructions register is entered null, qi in all digits. Such a micro-command does not specify any actions in the device and thus performs an idle cycle, during which special schemes store the address of the command whose reception was blocked in the micro-register register, as well as the contents of some other registers, for example, the address of the storage block ty), which is part of the processing device. Clock signals to the main units of the device in the idle cycle are not received. A similar idle cycle is performed after the completion of the microprogram processing the request from the I / O unit, during which the additional clock cycles to the main units of the processing unit are also blocked and the address is restored - the recalled microcommand, as well as other information related to the interrupted firmware. The presence of idle cycles when switching the hardware of the information processing device from the information processing mode to the I / O request processing mode and back decreases the overall system performance, especially in the case of frequent requests. As the right one, the most frequently executed firmware of the channels is rather short (4-10 minutes), In addition, the presence of zero combinations in each field of the microcommand is like. non-working (they do not have to call control signals in the system) leads to an increase in the memory size of the microcommand and its output register. It is also known a firmware processing device, in which the address of the next microcommand is formed by the result of the execution of the current one. This allows for the operation of the device not to take into account the specifics of the triggers and registers, the state of which changes every machine cycle. These devices are characterized by the presence of a high-capacity memory of mmkrokol-nd. The purpose of the invention is to increase the speed of the device and reduce the equipment. The proposed device differs from the known ones by introducing a buffer register connected via the first input to the output of the write control unit, whose inputs are connected respectively to the BTOpowry output of the analysis unit and to the third output of the firmware control unit, the first output of the buffer register is connected to the fourth input microprogram control unit and with the input of the block of triggers and registers, the output of which is connected to the second input of the buffer register, the third input and the second output of which are connected respectively but with the release of the arithmetic unit. The drawing shows a diagram of the proposed device for data processing. The device contains an arithmetic logic unit I, an I / O unit 2, a data storage unit 3, a firmware control unit 4, a query analysis unit 5, a trigger and register unit 6, a micro-command register 7, a buffer register 8, a write control unit 9. The output of the arithmetic logic unit is connected to the input of the input-output unit 2 and the input of the data storage unit 3. The output of the I / O unit is connected to the first input of the query analysis unit 5, the second input of which is connected to the first output of the 7 Mstando register, the second output of which is connected to the first input of the microprogramming control unit 4, the second and third inputs of which are connected respectively to the output of the arithmetic logic Block I and the first Query Analysis OUTPUT. The output of the firmware control block is connected to the input of the scroll register, the first input of the buffer register 8 is connected to the output of the record control block 9, the inputs of which are connected respectively to the second output of the block, query analysis and the third output of the myrco-comaid register. The first output of the buffer register is connected to the fourth input of the microprogram control unit and to the input of the trigger block and registers, the output of which is connected to the second input of the buffer register, the third input and the second output of which are connected respectively to the input and output of the arzhmeti1 co-logic unit. A: These are connected to the outputs of the I / O unit and the output of the data storage unit. The device for processing information is working as follows: I / O blocks place service requests at any time, and each block can place one of several requests. Each request has a specific priority. A device for processing information in each cycle of its work analyzes whether there is a request for service and it allocates a top priority to them. This function is performed by the query analysis block. In some of its states, for example, all service requests can be masked in the microprogram execution of the service request processing microprogram. This can be accomplished, for example, by a special microscopic discharge. In the absence of specified requests or the presence of secured requests for information processing in the current cycle, the address of the next kscrokand is specified by the current microcommand selected for the microcommand register 7. In in case of conditional generation of the address of the next qs command, the states of registers and triggers 6 are polled. If there is an unmasked request (with the highest priority) using block 5, query analysis iruets normal a form1fovanie address of the next mikpokovandy m indicate the current microinstruction and microinstruction address generated corresponding request. The microinstruction selected from the memory to the microinstructions register 7 is fully executed. At the end of the execution of the current microcommand, the query analysis block records the status of registers and triggers 6 into the buffer register 8 at the recording control block 9. In the next cycle of the data processing unit, the first microcode / MMA MMKponporpavMi will process the received service request, the address of the second microcommand will be determined by the previous first microcommand, which also blocks the query analysis block and blocks the change of the buffer register by appropriate block control records The blocking of the record in the buffer register is carried out until the information stored in the buffer register is overwritten by the arithmetic logic unit to the data storage unit. At the end of this procedure, the next running microcount, located in the microcommand register, can unlock the operation of the analysis block and thereby allow the processing of a new service request. Thus, the time of processing requests from the I / O unit is controlled by the firmware, and multi-level processing is possible when a higher priority request interrupts the lower-priority request service firmware. At the end of the execution of the service request firmware, information from the corresponding cells of the storage unit is transmitted through the arithmetic logic unit to the buffer register and then to the trigger and register unit. These transfers are controlled by one or more micro-instructions, depending on the specific structure of the data processing device. At the time of the transfer of information from the storage unit to the trigger unit and the registers of the m-commands that perform this transfer, the operation of the query analysis unit is also prohibited. Along with information on the current state of the block of triggers and,

the registers in the data storage unit also stores the address of the microcoland of the interrupted firmware;

The means of fixing such an address and its transmission path to the storage unit and back are not indicated in the drawing. Such a transfer can be controlled by the microprogram,

In accordance with the specified rules of operation of the firmware device, the address of the interrupted microprogram is restored first, and in the next cycle of the device, the contents of the block of triggers and registers are restored, which change their state each cycle,

The proposed device eliminates the need for idle cycles when switching from data processing mode to I / O request processing mode, which significantly increases the overall system performance compared to known devices and increases the peak (maximum) speed of the I / O units. . The cost of the additional input equipment (buffer register, recording unit, and several cells in the data storage unit) is significantly lower compared to known devices that trip the memory size of the commands, and create a permanent memory. (100-200 bits) with the speed required for a data processing device, given performance, may be impossible or entail a high cost of the device.

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INVENTION

An information processing device comprising an arithmetic unit connected to an input / output unit and a data storage unit, a microprogramme control unit, an analysis unit,

requests, a block of triggers and registers, a microcommand register, the output of an I / O unit connected to the first input of the query analysis unit, the second input

which is connected to the first output of the register of microinstructions, the second output of which is connected to the first input of the M1 control unit, the second and third inputs of which are connected respectively to the output of the arithmetic logic unit and the first output of the query analysis block, the output of the mdio unit

The control is connected to the input of the micro-command register, characterized in that, in order to increase productivity and reduce equipment, a buffer register is connected to it that is connected to the output from the first input. write control block whose inputs are connected respectively to the second output of the query analysis block and to the third / y

the output of the microprogrammed control unit 7, the first output of the buffer register is connected to the fourth input of the microprogrammed control unit and to the input of the trigger block and registers whose output is connected to the second input of the buffer register, the third input and the second output of which are connected respectively to the output and the arithmetic logic input block.

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