SU1365088A1 - Device for interfacing trunk lines - Google Patents

Abstract

The invention relates to computing and can be used in the design of multiprocessor computing systems. The aim of the invention is to increase the reliability of the device by optimizing the control. The device contains the first to fourth blocks of elements And 1,2,3,4, the exchange register 5, a group of 8 control units by module, a health register 9, a microprogram control unit 10, a group of 11 elements I. The device transmits information between two trunk lines mi, carried out its full control. 3 il.

Description

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The invention relates to computing technology and can be used in the design of multiprocessor computing complexes.

The purpose of the invention is to increase the reliability of the device by optimizing the control.

FIG. 1 is a block diagram of the device; FIG. 2 is a diagram of control units; FIG. 3 is a schematic diagram of a firmware control unit.

The device contains (Fig. 1) from the first to the fourth blocks of elements AND 1 - A, register 5 of exchange with group 6 information and rpynnovi 7 control bits, group 8 of control units modulo, register 9 of health, unit 10 of microprogram control, group 11 elements And, besides, information buses of the second 12 and first 13 highways are shown, state bus 14, tires 15,16 and 17,18 accompanying data and polling the second and first highways input 19 of the device mode setting, output 20 of the device availability.

The modulo control unit 8 contains (FIG. 2) an adder 21 modulo two, a comparison element 22.

The firmware control unit 10 contains (Fig. 3) a delay element 23, an OR element 24, a decoder 25, a fixed memory block 26, an address register 27.

The device works as follows.

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a press from the register 5 of the exchange of the Black block 3 to the same highway; send information from the second information highway 12 through block 2 to register 5 and return the contents from the exchange register 5 through block 4 to highway 12; transfer of address-numeric information from trunk 13 through exchange register 5 to trunk 12 with control of (byte-by-passing) groups of information transmitted in control blocks 8 and analysis of the health of the device in block 10; transferring address information from trunk 13 via exchange register 5 to trunk 12 and returning numerical information from trunk 12 through exchange register 5 to trunk 13 with group control (byte-by-by) all transmissions in blocks 8 and analyzing the health of the device in block 10; transfer of the control word from the highway 13 through one of the groups of the exchange register 5 to the highway 12 and the exchange of address-numeric information between the highways, carried out on this group.

The first two modes are check. With their help, it is carried out a check of the serviceability of the equipment of highways, transmissions and the exchange register.

The third and fourth modes are working.

The latter mode is a backup mode and is used to perform a byte transfer (or serial code exchange) between trunks over the first group of information bits of the exchange register, in the case of fixes

The code specifying the mode of operation of the device by means of the fault monitoring means goes to the fourth input of block 10 and is stored in the upper bits of the register 27 of this block, it is assumed that each of the information highways is involved in its processor, and one of the processors The first information trunk is the master, the other is the slave, and the mode code in block 10 is set by the master processor.

Depending on the code fixed in the high-order bits of the address register 27, it is possible to implement one of the following exchange modes between pc1H1strom 5 and highways 13 and 12: sending information from the first highway 13 via iiiioK 1 and ptM HC ip 3 and returning odernosti in one or more groups of programs, except the first. In this mode, the exchange begins by transmitting the control word over the bus 13 through the g register of the exchange to the bus 12, while the direction of the exchange is also indicated in the transmitted control word.

After setting the appropriate mode, the first or second input of block 10 receives a signal taken from bus 18 or 16, which starts block 10 of firmware control. This signal, having passed through circuit 24 and decoder 25, is fed to the input of block 26 and causes reading of information from the storage cell at the address of the set mode. As a result, executive signals are read out at the outputs of block 26.

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When the first mode of operation is implemented, the executive signals appear on the first, second and third outputs of block 26. The signal generated at the third output 26 (first output of block 10) is fed to the second input of block 1 and transmits the code from bus 13 in the register 5. The signal read from the second output of block 26, is fed to the input +1 of the register 27 and increases by one the contents of this register. The signal taken from the first output of block 26 and delayed by element 23 at the time of completion of transients in register 27 and block 26 enters the first input of circuit 2A and performs a new interrogation of block 26 at the following address, as a result of which executive signals appear on the fifth, seventh and twelfth outputs of block 26. The signal generated at the fifth output of block 26 (third output of block 10) is fed to the second input of block 3 and transmits the code from register 5 to bus 13. Signal read from the seventh output unit 26 (fifth fifth exit unit 10) post paet on bus 17 and accompanying information issued to the bus 13. The signal taken from the output of the twelfth unit 26 performs the setting of register 27 to its original state. After that, the device is again ready to implement any mode of operation.

The operation of the device in the implementation of the second mode is similar to the operation of the device for the case considered. Interrogation of unit 10 is carried out by a sigal removed from the bus 16. The executive signals appear first on the second and then on the fourth and sixth outputs of the unit 10. Their functions and purpose are similar the functions and purpose of executive signals removed from the first, third and fifth outputs of block 10, with the difference that they are assigned to tires 12 and 15.

If the code corresponding to the third mode of operation is set at the fourth input of block 10, the interrogation signal received at the first input of block 10 from bus 18 causes reading of executive signals from the first, second and third outputs of block 26. These signals transmit the code from line 13 to register 5 increases

Register 27 and 1 polls block 26 at the new address. (This sequence of actions is described in detail when considering the first mode of operation.) After code is entered into register 5 for each group of register bits 5 using the node 21 of control unit 8, the module contains two modules of information bits of these groups and compare them in node 22 the results of the convolution with the value of the check bit of the corresponding group. The comparison results (for each group) from the outputs of blocks 8 arrive at the second inputs of the corresponding nodes 11, and the interrogation of block 26, performed at the new address, you The output of the executive signals at the first and tenth outputs of block 26. The last executive signal (signal from the eighth output of block 10) goes to the first inputs of nodes 11 and rewrites the state of the control results to the lower bits of the register 27 of block 10. The executive signal taken From the first output of the block 26 and delayed by the element 27, produces a new re-poll block 26.

If, as a result of the control, no faults were detected in any of the analyzed groups, then the lower code or the code of the corresponding health condition is entered in the lower bits of register 27. Re-polling of block 26 leads to the generation of actuating signals that control block 4 to transfer the code from register 5 to bus 12 and set register 27 to its initial state. The detection by the control circuits 8 of the discrepancy in the results of the comparison of the collapsed information on any group with the test bit of this group for one or several groups leads to the fact that in the register 27 from the nodes 11 there is a code that is different from the health state. Repeated polling of block 26 leads to the generation of actuating signals, which install the register 9 into the state indicating the number of the faulty group or groups and transmit the fault signal via bus 14.

The fourth mode of operation is similar to that considered and differs from it only in that in this mode the polling

control results are carried out twice. Once when the code is transmitted from trunk 13 to bus 12, another time during reverse transmission. Therefore, the completion of all transmissions sets the register 27 to the initial state, for which the executive signal from the twelfth output of block 26 is used. Moreover, several (not more than three) low bits of the register 27 for the third and fourth modes of operation ensure the operation of the device. The code is not entered into them from the output of the nodes 11.

The device can also function with some loss of speed. So, if blocks 10 and 9 detected a malfunction or malfunctions belonging not to the first group, it is possible to set the exchange operation mode using the information bits of the first group of the register 5. At the same time, the third and the fourth mode is based on the algorithms of the described modes. However, the transmissions between the Mistors are carried out in this case not by complete words, but byte-by-byte, and the results of control for failure of other groups are ignored.

Claims (1)

Invention Formula A device for interfacing the highways containing the exchange register, a group of control units modulo, the first to fourth blocks of the AND elements, the microprogram control block, and the first to the fourth outputs of the microprogramming control block are connected to the first inputs of the first to fourth blocks of the And elements, respectively the second inputs of the first and second blocks of elements AND in the device inputs for connecting respectively to the information buses of the first and second masters 0 five 0 five five 0 five 0 Rale, the outputs of the first and second blocks of elements And are connected to the first and second group information I the inputs of the exchange register, the first and second groups of information outputs of which are connected to the first inputs of the third, fourth blocks of I, respectively, whose outputs are the outputs of the device for connecting respectively to the information buses of the first and second highways, from the fifth to the seventh outputs of the microprogram control unit with the device outputs for connecting, respectively, to the data tracking buses to the state bus of the first and second highways, the first, second inputs of the logical conditions of the block firmware controls are the device inputs for connecting to the polling buses of the first and second highways, the i- group (i 1, p) of the information outputs and the output of the i-ro control bit of the exchange register are connected respectively to the first and second information inputs of the i-ro control unit modulo group, characterized in that, in order to increase the reliability of information transfer, a group of elements AND and a health register are entered into it, with the first inputs of elements AND of a group connected to the eighth output of the microprogram control unit No, the output of the i-ro control unit modulo the group is connected to the second input of the i-ro element AND group, the outputs of elements AND group are connected to the input group of logic conditions of the microprogram control unit, the ninth output of which is connected to the information input of the health register, the output of which is The device ready output, the third logic input of the firmware control block, is the input for setting the device mode. From control. fig.Z Compiled by S. Buruhin Editor M.Blanar Tehred L.Ssrlyukova Order 6611/42 Edition 704Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 FIG. Code realizable mode / about Proofreader S. Shekmar.