SU964620A1 - Multiplexer channel - Google Patents

Description

(5) MULTIPLEX CHANNEL

one

The invention relates to computing and can be used in computing systems with increased reliability.

Known computers with an I / O system are built on the basis of I / O channels, which, when performing an I / O operation, use the equipment of the central processor containing the communication unit with the RAM, memory, the microprogrammed control unit, the arithmetic logic unit interconnected by the inputs and outputs of the processor, a system of information, address and control (5 buses tl).

The disadvantage of these devices is the low performance of the central processor, since during the servicing of I / O operations 20 the processor does not process commands.

The closest technical solution to the invention is a multiplex channel comprising a firmware control unit, a memory communication unit, a register unit, a control register and an arithmetic unit, the output of which is connected via output data buses to the first input of the register unit and the input unit main memory, the first output and input-output of which are connected to the memory buses, and the second output - to the second and third input of the arithmetic unit through the input information buses, to which The input buses of the central processor are also connected, the first input of the microprogrammed control unit and the first output of the reGistrov block, the second and third inputs and outputs of which are connected to the information and control interface buses, and the fourth and fifth outputs respectively to the second input of the block firmware control and the first input of the control register, the output of which is connected to the third input of the firmware control unit, the first second, third and fourth outputs of which are connected respectively to the output by the CPUs, by the access buses, via the control buses with the fourth inputs of the arithmetic unit and the register block, through the constant buses with the first input of the arithmetic unit CZJ. The disadvantage of this multiplex channel is the low reliability of information processing, since in the process of performing an information I / O operation, the control of data transmission circuits carried out even does not allow to detect multiple errors. The purpose of the invention is to increase the reliability of processing information of a multiplex channel. The goal is achieved by the fact that in a multiplex channel containing a microprogrammed control unit, a main memory communication unit, a register unit, a control register and an arithmetic unit, the output of which is connected to the first input of the main memory unit and the input of the main memory communication unit. and the input and output of which are connected to the corresponding buses with the memory of the device, the first information input of the arithmetic unit. connected to the second output of the communication unit with the RAM, input buses of the central processor unit, the first input of the firmware control unit and the first output of the register block, the second and third inputs and outputs of which are connected respectively to the information and control I / O interface buses of the device , and the fourth and fifth outputs, respectively, with the second input of the firmware control unit and the first control register input, the output of which is connected to the third input of the microprogram control, the first and second outputs of which are connected respectively with the output buses of the central processor of the device and output buses of the device, and the third output with the control input of the arithmetic unit and the fourth input of the block of registers, the switching unit, the OR element, trig group geers, a group of AND-OR elements and an error trigger, and a single error trigger output is connected to the second control register input, the installation and reset inputs of the error trigger are connected respectively to the output of the IL element Both, and to the third output of the microprogram control block, the first and second inputs of the AND-OR group elements, the fault inputs of the group triggers and the first input of the switching unit, the second and third inputs of which are connected respectively to the fourth output of the microprogram control unit and the second output block z with RAM, the first output with the second information input of the arithmetic unit, and the second output with the third information input of the arithmetic unit and. the third inputs of the AND-OR group, the fourth inputs and outputs of which are connected respectively to the output of the arithmetic unit and the counting inputs of the corresponding group triggers, the unit outputs of which are connected to the input group of the OR element. FIG. 1 is a block diagram of a multiplex channel; in fig. 2 is a functional diagram of the input selection block. The multiplex channel (Fig. 1) contains a microprogram control unit 1, a random access memory unit 2, an arithmetic unit 3, a register register unit 5, a control register 5, a switching unit 6, OR element 7, group triggers 8 (the number of triggers is determined by channel information stream), AND-OR 9 elements, trigger 10 errors. FIG. 1 designates input and output buses of the device for communication with the processor and random-access memory: input buses 11 of the central processor, bus 12 exchanges with random-access memory, output buses 13 of the central processor, bus 1 circulation, internal buses of the device; control buses 15, bus constants 16 and information buses 17 and 18, as well as device buses for communicating with I / O devices; information and control information buses 19 of the interface, control buses 20 of the interface, bus 21 of the first input, bus 22 of the second input. . The microprogram control unit 1 ensures the automatic operation of the multiplex channel in accordance with the set microprograms. Unit 1 contains (Fig. 1) a micro-command register 23, including address fields 23.1, control fields 23.2 and field 23.3, control memory 2k and control address register 25. Block 2 of RAM communication serves for the exchange of information between the RAM and the multiplex channel. Block 2 contains the register 26 of the address of the operative memory T1 and the register 27 of the data of the RAM. The arithmetic unit 3. is designed to process information entering the multiplex channel from the central processor, RAM, and external devices, and contains (Fig. 1) input registers 28.1 and 28.2, the arithmetic logic unit 29, built on elements of the type SPW, and multiplexers 30, the number of which is determined by the size of the information flow in the channel. . The registers unit C is designed for intermediate storage of the current channel control word, control of communication and information exchange between the channel and external devices, and contains (Fig. 1) the channel control word 32 (Channel Control Register) 32, the channel control register 32, the register 33 subscriber controls, register 3 / output information, output information register 35. The switching unit 6 serves to select the source register supplied to the input of the arithmetic unit 3 depending on the mode of operation of the multiplex channel, i.e., information processing or control. Block 6 contains (Fig. 2) the first group of elements AND-NOT Zb-, the second group of elements AND-NOT kl-kk, the group of multiplexers of the first operand and the group of multiplexers 6, the second operand (the number of multiplexers in the group corresponds to the size of the information flow in the channel). The multiplex channel works in a near manner. The I / O operation is controlled by a channel program consisting of a series of channel control words. Channel control words contain all the necessary information to perform an I / O operation, namely: operation code, data address, byte count, and special flags modifying the channel program. The channel program is stored in the RAM and, as necessary, the next channel control word is retrieved from the RAM (not shown). Further control of the I / O operation is performed under the control of this channel control word, which is called current. A channel forms a control word for each I / O operation and stores its moment of communication with the device on the channel registers, and during the entire I / O operation in a special context by a memory operative called multiplexed memory. The first control word of the channel of the channel program is retrieved from the RAM by the initiative of the central processor (not shown). To do this, the latter issues a special command that contains the channel address and the address of the external device for which the I / O operation should be started. The multiplex channel receives the command via the buses 11 and generates the starting address of the service firmware of this command in the control memory address register 25. According to the contents of register 25, information from control memory 2 is read out and entered into register 23 of micro-instructions. The contents of register 23 form the address of the next microcommand and control the operation of the channel during one machine cycle. Under the command service firmware, the control word is read from the memory to the address stored in register 2b, via bus 12 to memory register 27, and through information bus 18 and multiplexers 30 is provided to information bus 17 for writing to register 31 current USK. After obtaining the necessary control information, the channel performs an initial sample of the addressable I / O device (not shown). At. This transfer of the device address, command code and byte of the initial state of the addressable device control register 32 and register 33. The installation of the corresponding triggers in these registers is performed by firmware via bus 15 and hardware through bus 20. After the initial sampling of the input-output device is completed, the register contents 31 of the current ACC enters the information buses 19 and through the multiplexers 30 and the information strings 17 is entered into the register 27, the contents of which are written to the multiplex memory via the control signal from the bus 1 The address from register 2b, whose content is determined by the address of the input / output device. Then the channel informs the central processor about the result of starting the I / O device through the bus 13 by setting the corresponding result code. From this moment on, the central processor and the channel start working in parallel according to their program. When it is ready to receive or transmit data bytes, the I / O device issues a special signal to the control buses 20 of the interface, on which the corresponding trigger in register 33 of the subscriber is set. According to the state of this trigger, the register 25 of the control memory address forms the starting address of the data service microprogram, which: reads the control word from the multiplexed memory area defined by the address of this I / O device; performs information transfer cycles between the processor’s RAM and the I / O device; Modifies the data address and byte count for the number of bytes transferred; stores the modified control word of the device in the old multiplexed memory area. The data service firmware is repeated as many times as the data bytes need to be transferred between the I / O device and the main memory in one connection to the channel. When executing a read command, the data from the I / O device is passed through the interface information buses 19 to the input information register 35. The contents of register 35 through the input information buses 18 are fed to the information inputs of multiplexers 30, to the control inputs of which a control signal is received from the buses 15, passing this information to the information buses 17 for writing to the memory data register 27. The address of the data from the register 31 of the current UMC along the described chain is transferred to the register 26 of the address of the operational memory. On the control signal from the transfer bus to the register 27, the information is written into the operational memory via the bus 12. After the data is written into the operational memory, the data address and the byte counter are modified by the number of transmitted bytes. For this purpose, the address of the data from the register 31 of the current UIC on information buses 18 is fed to the information outputs of multiplexers 46, and the modifying constant is fed to the information inputs of multiplexers 5 via buses 16 constants. The control signals from busses 15, coming through the N-Zb-38 and I-NES 42-4t elements to the control inputs of multiplexers 6 and directly to the control inputs of multiplexers S, allow the issuance of this information with the output of multiplexers to registers 28.1 and 28.2. The result of the modification from the output of the arithmetic unit 29 through the multiplexers 30, under the control of the signal from the busses 15, goes to the information buses 17 for writing to the register 31. The modification of the byte counter is performed similarly to the modification of the data address. The write command differs from the read command in that the control signal from buses 1 4 reads data from the RAM through bus 12 and is stored in register 27. Data from register 27 through data buses 18, multiplexers 30 and data buses. 17 are transmitted to re: output information hr, from which they are fed to the I / O device via the information bus L9 of the interface. The deviation from the norm of information transmitted over the information buses of the channel, as well as violation of the requirements for the duration of the sequences of signals transmitted between the channel and I / O devices, are recorded in control register 5, in which if information is detected on the information buses or even violations in the sequences the control signals of the interface are set to one trigger state corresponding to this error. This trigger in register 25 forms the starting address of the hardware error processing firmware, which informs the central processor about

reason for stopping the I / O operation.

During information processing in the information channel, the information bus 17 enters in parallel to one of the registers of block A through elements 2И-OR 9 to the counting inputs of triggers 8 via the control signal from the bus 15 Contents of the register of the block i after entering information into it information buses 18, block 6, buses 22 and elements 9 to the same counting inputs of the triggers 8. In the absence of an error in the register and the information transfer circuits, the triggers B must be in the zero state. If there is a malfunction, the triggers corresponding to the bad bits will be in one state and through the element OR 7 will cause the trigger one 10 to be set to error, which will set the corresponding error sign in the control register 5, and then by the control signal from the tires 15 triggers B and 10 will be reset.

As an example, let us consider the transfer of the address of the data from the register 31 of the current UMC to the register 2b of the address of the data of the operational memory and its modification. For this purpose, the address of the data from register 31 through information buses 1B, multiplexers 30 and buses 17 information simultaneously enters register 26 and through elements 9 to the counting inputs of triggers B. After receiving the information, the contents of register 2b go through information buses 1B to the information inputs of multiplexers 6 The control inputs of these multiplexers receive control signals from the bus -15 through the AND-NOT and AND-NOT L2-A elements, which allow the output of the register 26 to the 22 busses to be entered through the elements 9 to the counting inputs. Triggers V.

When modifying, the data address is received from register 3 via information buses 1B to the information inputs of multiplexers 6, and the control SI that allows the output of the data address to register 28.2 is received through the elements AND-NOT Zb-38 and AND-NOT k2 -ki from bus 15 to control inputs of the same multiplexers. The constant for modifying arrives in register 28.G from bus 16 via multiplexers k. The result of the modification through the multiplexers 30 information buses 17 is entered simultaneously into the register 31 of the current UCS and through the elements AND-OR 9 to the counting inputs of the triggers B. After receiving the information, the data address from the 3V register is again via the information buses 1B, block 7, buses 22 and the elements AND - OR 9 is applied to the counting inputs of the flip-flops 8, as previously described. If there is a malfunction, the triggers corresponding to the failed bits will be in one state and installed via the OR 7 element trigger 10 error, which will set in the control 5. register corresponding to the error acknowledgment. This symptom will cause the hardware error handling firmware to report the error to the central processor.

Thus, the proposed multiplex channel allows detecting errors of any multiplicity in the information flows inside the channel, which provides an increase in the reliability of processing.

Claims (2)

Invention Formula A multiplex channel containing a firmware control block, a memory communication unit, a register unit, a control register and an arithmetic unit whose output is connected to the first input of the register unit and the input of the memory communication unit, the first output and input-output connected to the corresponding communication buses with the device’s RAM, the first information input of the arithmetic unit is connected with the second output of the communication unit with the RAM, the input buses of the device’s central processor, The first input of the firmware control block and the first output of the register block, the second and third inputs and outputs of which are connected respectively to the information and control buses of the device I / O interface, and the fourth and fifth outputs, respectively, to the second input of the firmware control block and the first register input control whose output is connected to the third input of the firmware control unit, the first and second outputs of which are connected respectively to the output buses of the central processor unit the third output — with the control input of the arithmetic block and the fourth input of the register block — about the fact that, in order to increase the reliability of processing information of the multiplex channel, the switching unit, the OR element, the trigger group, the AND-OR element group and the error trigger are entered, the single error trigger output is connected to the second input of the control register, the installation and fault inputs of the error trigger are connected respectively to the output of the OR element and to the third output of the firmware control unit, the first and second inputs of the AND-OR group elements, the fault inputs of the group triggers and the first input of the switching unit, the second and third inputs of which are connected respectively to the fourth output of the firmware control unit and the second output of the communication unit with operational memory Tew, the first output - with the second information input of the arithmetic unit, and the second output - with the third information input of the arithmetic unit and the third inputs of the AND-OR group elements, the fourth inputs and output s which are respectively connected to the output of the arithmetic and counting -block respective inputs of flip-flops. groups, single outputs of which are connected to the group of inputs of the elements OR. Sources of information taken into account in the examination of 1. Electronic computer EC-1050. M., -Statistics, 1976, Ch. four. . 2. US patent number Z "53b00, cl. G About F 3/0, publ. 1969 (prototype).