SU708342A1 - Data exchange arrangement - Google Patents

Description

one

The invention relates to the field of computing, in particular, to devices of exchange and can be used in data processing systems.

A device for exchanging data is known, comprising a channel switch, an address counter, a switch, a channel number switch, communication registers, a priority selection channel of the termination channel o6i change, a priority selection channel of the sync signal channels, a control unit l.

A disadvantage of the known device is the need for significant equipment costs.

The closest to the invention in technical essence and the achieved result is a device for data exchange, containing a main memory block, the input / output of which is connected to the first input - the output of the buffer memory block, the control word receiving block, the output of which is connected to the register input the final address and the first input of the current address register, the exchange control block, the first inputs and outputs of which are connected respectively to the output of the comparison circuit and the first input of the main memory block, the interface block, the first the input and output of which are, respectively, the input and output of the device, the output of the end address register, the first and second outputs of the current address register are connected respectively to the first and second inputs of the comparison circuit and the cf second input of the main memory unit.

The disadvantage of this device is that it requires significant equipment costs for its implementation and does not allow selective transmission of various parts of the data word.

The purpose of the invention is to reduce the equipment and expand the functional capabilities due to the selective transmission of various parts of the word length.

The unallocated goal is achieved by the fact that the device contains switch-byte chords, the second one being the output of the block

exchange control units are connected respectively to the second input of the current address register, to the first input of the buffer memory block, to the first input of the byte switch, to the second input of the interface unit, input-output, the second and third outputs of the interface unit are connected respectively to the second input- the output of the buffer memory block, with the input of the control word receiving block, with the second input of the byte switch, the first second outputs of which are connected respectively to the second input of the control block and deceived with the second input of the buffer pa block ty.

The block diagram of the device is shown in the drawing.

The device for data exchange contains a main memory block 1, a switch of 2 bytes, a conjugate block 3, a buffer memory block 4, a control word receiving block 5, a destination address register B, a current address register 7, a comparison circuit 8, a control block 9 exchange, input 10, output 11.

 The device works as follows.

The buffer memory block 4 is a register with input and output logic, the number of bits of which is equal to the word digits of block 1, the input and output of each register bit are connected to block 1 by the data bus and through logic elements (in the drawing does not show ) - with block 3 of the conjugation, the second inputs of which are combined byte by byte by uravl by four inputs, and serves to receive and output byte-by-byte data in accordance with the signals received by the control from the switch 2.

The control word receiving unit 5, consisting of AND-NOT logical elements, is used to receive the address word of the control word in the registers of the final 6 and the current 7 addresses.

The comparison circuit 8 is made on the I-NB logical elements and is intended to issue a control signal to the exchange control unit 9 when the addresses in the registers 6 and 7 match.

The exchange control unit 9 consists of triggers, registers, counters, decoders and logical elements I-NOT, I-4 LI-NB and is designed to organize the operation of the entire device in accordance with the data exchange program performed in a circuit and placed in the named block.

The interface unit 3 consists of information reception-output registers, AND-NOT logical elements and is an input-output interface for a computer.

The 2 byte switchboard consists of triggers, the NAND logic gates, is a microprogrammed automat and is intended to issue control signals to block 4 in accordance with the received positional code.

When a computer calls the exchange device, in block 3, input 10 receives a control word.

The address part of the control word is received in block 5, and the part of the control word, which is a positional code indicating which bytes of each word read from memory block 1, must be entered into the computational interface in the Data transfer from the device to the computer mode. and what bytes in the words of the array of memory block 1 must be replaced when the mode Data transfer from the computer to the device is transferred to switch 2.

The data is exchanged according to the requests, the input from block 9 to block 1. With a single call to block 1 of the memory, the word is read from it in accordance with the address contained in register 7 and entered into block 4. Block 2, in which the position code of the reception or output bytes is located, alternately sending signals to the control inputs of block 4 in accordance with the code.

The mode of issuing or receiving bytes is determined by the control word and is specified by block 9.

For example, in the Transfer data from device to computer mode and positional code of bytes 10011100 located in switch 2, it will allow 1, 4, 5, 6 bytes of transmission of each word of the input array of memory 1 to be transferred through unit 3 to the computer where switch 2 working asynchronously and time, for the analysis of the position code is not required.

The data exchange of the device with the computer is performed byte-by-byte according to the address contained in register 7.

Claims (2)

In the process of data exchange, block 9 modifies the address. The data exchange continues until the current and final addresses in registers 7 and 6 coincide. In this case, the comparison circuit 8 outputs a signal to the block 9 vol. termination of the data exchange and sets the device in the initial state. The invention The device for data exchange, containing the main memory block, the input of which is connected to the first input of the output of the buffer memory block, the control word receiving block, the output of which is connected to the input of the end address register and the first input of the current address register, the exchange control block , the first input and output of which is connected 9 ° responsibly with the output of the comparison circuit and with the first input of the main memory unit, the interface unit, the first input and output of which are respectively the input and output of the device TWA, the output register of the final address, the first and second outputs of the current address register are connected respectively to the first and second inputs of the comparison circuit and the second input of the main memory block, characterized in that, in order to reduce the equipment and expand the functionality due to selective transmission of various parts of the data word, it contains a byte switch, and the second - fifth outputs of the exchange control block are connected respectively to the second input of the current address register, to the first input of the buffer block memory, with the first input of the byte switch, with the second input of the interface unit, input – output, the second and third outputs of the interface unit are connected respectively with the second input-output tuio of the buffer memory, with the input of the control word receiving unit, with the second the input of the byte switch, the first, second outputs of which are connected respectively to the second input of the exchange control unit and to the second input of the buffer memory unit. Sources of information taken into account in the examination 1. USSR author's certificate hfi 5О6017, cl. in About F 3 / O4, 1973. 2. USSR author's certificate N 506847, cl. G 06 F 3/04, 1974 (prototype).