SU947849A1 - Interface - Google Patents

Description

The invention relates to computing and can be used in computing systems for interfacing a digital computer with external devices.

A device for communicating a control computer with peripheral devices is known, comprising an exchange register connected to peripheral registers by two-way communication, a priority selection unit, a control unit and a switch 1.

The main drawback of the device is limited functionality, which excludes simultaneous data exchange of several external devices (subscribers) with the exchange processor;

The closest technical solution to the present invention is an interface device comprising subscriber subchannels, a priority block, a synchronization block, an exchange register, the first input and output of which are respectively information input and output of the device, and the exchange control block, the first input and output of which are respectively. ,

The input and output of the device, the second input and output are connected respectively to the first output and the input of the synchronization unit, the second and third outputs of which are connected respectively to the first input of the subscriber subchannels and the control input of the priority block, request inputs and output gates

10 of which are connected respectively with the first outputs and the second inputs of the respective subchannels of subscribers, in addition, it contains a program readiness register, connected

15 information input and output respectively to the second output and the input of the exchange register, the control input to the fourth output of the synchronization unit, and the control outputs to the third inputs of the respective subscriber subscribers, the information switch and the control unit modulo connected to the first input and output respectively with the third

25 output and input of the exchange register, and the second and third inputs, respectively, with the third output of the exchange control unit and the fifth output of the synchronization unit, the sixth output

30 of which is connected to the control input of the information switch, the information input and the output of which are connected respectively to the fourth output and the exchange register input connected by the fifth input to the fourth output of the exchange control block, and the inputs and outputs of the information input groups and outputs and group outputs address inputs - corresponding to the fourth inputs, the second and third inputs of the corresponding subscriber subscribers, and the subscriber subchannel contains a register of service signals, connected by input and output With the first output and input of the control unit, the type transfer switch connected to the input and output, respectively, with the fifth output and input of the subchannel register, the second input and output of which are respectively the fourth input and the second output of the subchannel, the And element, the first input of which is the third input of the subchannel, and the output is connected to the second input of the control node, the third and fourth outputs of which are connected respectively to the second input of the transfer type switch and the third input of the subchannel exchange register, and the fifth the sixth, respectively, with the third output of the subchannel and the input of the ready trigger, the output connected to the first output of the subchannel, and the OR element, whose inputs are the first and second inputs of the subchannel, respectively, and the output connected to the input of the And 2 element. The disadvantage of this device is low speed and large hardware costs due to the implementation of a multiplexed mode of exchange with various subscribers by switching and sequential transmission of the subscriber number and then the actual word of information. The purpose of the invention is to increase the speed of the device due to the organization of the parallel issue of the number of the senior subscriber and the word information, as well as the reduction of hardware costs. The goal is achieved by the fact that the device containing the exchange register and the exchange control block, the first inputs and outputs of which are respectively the information and control inputs and outputs of the device, the priority block, the module control module, the first input and output of which are connected respectively to the second the output and input of the exchange register, the third input and output of which are connected respectively to the information output and the input of the register of readiness of programs, the second input and output of the exchange control block are connected respectively with the first output and input of the microcommand formation unit, and the third and fourth outputs, respectively, with the second input of the control unit modulo and quarter input of the exchange register, a group of subscriber subchannels, the input and output groups of which are the corresponding input and output groups of the device, the first inputs connected to the second output of the micro-command formation unit, the first outputs and the second inputs, respectively, with the groups of inputs and outputs of the priority block, and the third inputs, with the output group of the readiness register of the program m, the third, fourth and fifth outputs of the microcommand formation unit are connected respectively to the input of the priority block, the control input of the program readiness block and the third input of the control unit modulo, two groups of OR elements are entered, the second and third outputs of the group subscribers' subchannels are connected respectively the inputs of the OR elements of the first and second groups, and the fourth inputs - to the third output of the exchange register, the third input of which is connected to the outputs of the OR elements of the first group, the outputs of the OR elements of the second group are connected enes to the address output device. Figure 1 presents the block diagram of the device; FIG. 2 is a block diagram of a subscriber subchannel; Figures 3 to 5 illustrate functional diagrams of a micro-command formation unit, a subscriber sub-channel control unit and an exchange control block, respectively. The device (Fig. 1) contains the exchange register 1, the exchange control unit 2, the microinstruction generating unit 3, the priority block 4, the group of 5 subchannels of subscribers, the control unit modulo, the program readiness register 7, the elements OR 8 and 9 of the second and first groups. The device interfaces with the exchange processor 10 and with subscribers (external devices) 11. Subchannels 5 subscribers (FIG. 2) are similar to those described in 2 and contain a subchannel exchange register 12, a control node 13, an overhead register 14, a transfer switch 15, a trigger 16, subchannel ready, element 17, and element 18. Micro-command generation unit 3, control unit 13 and exchange control unit 2 can be implemented on the basis of a microprogram control principle. Each of them contains (FIGS. 3-5) a constant memory unit 19, a micro-command address decoder 20, a micro-command address counter 21, a micro-command address modification modification 22.

Blocks 3 and 2 and node 13 operate in accordance with the program recorded in block 19 of the item of permanent memory. The processing of external signals is performed in the counter 22.

The device works as follows.

The processor 10 at the beginning of operation issues a mode command to the exchange register 1, which is decoded by block 2, which starts block 3 in turn, preparing it for autonomous work on receiving and issuing information.

The processor 10 then outputs the program word state, which is transmitted through register 1 to register 7, where it is stored for the entire exchange time, until the register 7 is changed. After writing to register 7, unit 3 starts the subchannels by applying a signal to the inputs of the elements OR 18 The output signal from the element OR 18 passes through the element AND 17 only if there is a signal from the corresponding register bit 7 to the element AND 17. In this case, the signal through the element 17 goes to the node 13, initiating the autonomous operation of the subchannel.

The launched subchannels 5 operate simultaneously and independently, issuing (or receiving) one word of information to (or from) the external device in conjunction with a specific time diagram of the latter. Receiving or issuing the word subchannels ends by setting the trigger state 16 to a single state and passing the subchannel 5 to the idle state of communication with register 1.

The exchange of information subchannels 5, ready for exchange with the processor 10, is as follows.

Block 3, giving a signal to block 4, selects the number of the senior subchannel from among those that have set their readiness. Block 4 enables one subchannel 5 to work, issuing a signal through the OR 18 element and the AND 17 element to the node 13. The started node 13 outputs 10 through the element OR 8 address of the subchannel and at the same time the information word from the register 12 of the subchannel exchange through the element OR 9 and the register 1 of the exchange to the processor 10. In the case of receiving the information word from the processor 10 enters the register 12 through the register 1 of the exchange.

The block b, under the influence of the signal from block 2, performs control of the information word, for example, modulo three when receiving information from processor 10 and generating control bits modulo three when transmitting information to the exchange processor. In addition, block 6, under the influence of a signal from block 3, produces control or generation of control bits in the information word when exchanged with an external device in accordance with the specific type of control received in this external device. After the end of the cycle, including the simultaneous transmission of different types of subchannel numbers and information words, the exchange cycle is repeated in the general case with the participation of another subchannel. This mode is typical for multiplex exchange with the sharing of kanash time between many external devices and the exchange processor.

Thus, the device provides simultaneous operation of external devices with the exchange processor, while reducing the time of each cycle due to the simultaneous transmission of the subchannel number and the actual word, which causes an increase in the speed of the device. In addition, there is no information switch in the device, which is in the prototype.

Claims (2)

Invention Formula A device for interfacing, containing the exchange register and the exchange control block, the first inputs and outputs of which are respectively information and control inputs and outputs of the device, a priority block, a modulo control unit the first input and output of which are connected respectively to the second output and register input exchange, the third input and output of which are connected respectively to the information output and the input of the register of readiness of programs, the second input and output of the exchange control block are connected respectively to the nepBEJM output and the input of the microinstructor formation unit, and the third and fourth outputs, respectively, with the second input of the control unit modulo and the fourth input of the exchange register, a group of subscribers' subchannels, the input and output groups of which are the corresponding input and output groups of the device, the first inputs are connected to the second output of the microinstruction formation unit, the first outputs and the second inputs - with the input and output groups of the priority block, respectively, and the third inputs - with the output group of the program readiness register, the third fourth and n This output of the micro-command formation unit is connected respectively to the input of the priority block, the control input of the program readiness register and the third control unit input modulo, characterized in that, in order to improve the speed of the device, two groups are entered into it elements. OR, the second and third outputs of the subchannels of the subscribers of the group are connected respectively to the inputs of the elements OR first and second; a swarm of groups, and the fourth inputs - to the third output of the exchange register, the third input of which is connected to the outputs of the elements OR of the first group, the outputs of the elements OR of the second group Yodklyucheny to the address output of the device. Sources of information taken into account in the examination 1. The author's certificate of the USSR 524176, cl. G About F 3/04, 1974. 2. Authors certificate of the USSR 736086, cl. G 06 F 3/04, 1978 (prototype). f-tf CC of Cpue.i Hl5L / 7 nineteen 20 21 / f n7 AJ FROM