SU1285486A1 - Switching device - Google Patents

Abstract

The invention relates to computing and can be used to build data exchange subsystems in multi-machine computing systems. The invention aims to increase throughput and expand functional functions. .ga „and tenderness of the device due to the possibility of choosing the least loaded subscriber. The device contains groups of blocks 1, 2 bus drivers, switching blocks 3, counters 4 and blocks 5 for determining the minimum number. Counters 4 store the codes for the current numbers of occupied by the cells in the input buffers of the switched machines. The counter 4, in which the minimum number was recorded before the device started operation, will generate a signal earlier than the other counters 4 that initiate the exchange of the external subscriber with the computer, the number of which is equal to the counter number, 2C. f-ly, 3 ill. (L with

Description

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The invention relates to computing and can be used to build data exchange subsystems in multi-machine computing systems.

The purpose of the invention is to increase the capacity and expand the functionality of the device by providing the ability to select the least loaded subscriber.

Figure 1 presents the block diagram of the switching device; in Fig. 2, a functional diagram of the switching block on Lig.W is a functional circuit of a block for determining the minimum number.

The device contains the first group of blocks 1 bus drivers, the second group of blocks 2 bus drivers, switching blocks 3, counters 4 and blocks 5 for determining the minimum number.

The device has data addresses of the first 6 and second 7 groups, resolution inputs of the first 8 and second 9 groups, sample inputs of the first 10 and second 11 groups, data outputs of the first 12 and second 13 groups, query outputs of the first 14 and second 15 groups, outputs ready For the first 16 and second J / groups, inputs 18 and release 19.

The switching unit 3 contains two 20 and 21, two circuits 22 and 23 comparing j, two groups of 24 and 25 elements, two elements of RSHI 26 and 27, two triggers 28 and 29, six elements of AND 30-35 and a chip of HE 36-39.

The switching unit 3 has the first 40 and second 41 inputs of the data address, the first 42 and second 43 readiness inputs, request control input 44, the first 45 and second 46 sample inputs, the first 47 and second 48 resolution outputs, the first 49 and second 50 request outputs , the first 51 and second 52 resolution inputs, the first 53 and second 54 data outputs,.

The minimum number determining unit 5 contains counters 55, triggers 56, one-shot 57, multi-input element 58, three-input elements 59, accessibility register 60, generation, torus 61, delay element 62, characteristic register 63 and comparison circuit 64.

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The minimum number determining unit 3 has information inputs 65, a sign input 66 and a request control outputs 67.

The device can operate in three modes: in the exchange mode at an address initiated by the computer (VM), in the exchange mode at the address initiated by an external subscriber (BA) and in the exchange mode without an address initiated by VA, the latter mode assumes the direction of exchange - recording data in the VM.

The device works as follows.

In the initial state in each block 5, the triggers 56 are set to the zero state and the unit level from the output of the multi-input element And 58 is fed to the input (N + l) -ro of the three-input element And 59 and to the inputs of the other elements And 59. In the counters 4 recorded binary codes equal to the current-. The number of occupied waiting places in the input buffer memory of the corresponding VMs. Registers 20 and 21 of the switching unit 3, located at the intersection of the j-th row and the i-ro column of the matrix, contain the addresses, respectively, j-ro ro j of the j-th BMi. with the address code of a single VM.

In the exchange mode by address initiated by the VM, data exchange, for example, between the jth VM and J-M BA starts from the jth BM address to the j-ro BA address and the sample control signal, respectively, to the data address and device sample inputs. In this case, the sampling signal arrives at the second input of the AND element 32, and the address code goes to the second information input of the comparison circuit 22 of each switching unit 3 of the i-th matrix column. If, in the comparison circuit 22, the received address is compared with the contents of the first register 20, then the unit level arrives at the first input of the AND element 32, the output of which sets the first trigger 28 to the unit state, the unit level from whose output goes to the j-ro request input unit 1 of the first group and then from the device request output as a device request signal as a signal

the request is issued to the i-th VA. In the case of non-matching of the addresses or when comparing them, but if there is a zero level at the second input of the AND 32 element, the request trigger 28 is not set to one. This eliminates the possibility of the j-ro VA being intercepted by a computer with a higher priority until

In the address exchange mode initiated by the BA, data exchange, for example, between the J-M BA and the j-th VM begins with the issuance of the J-M BA of the j-th VM address and the control signal of the sample, respectively, at the data address inputs and sample of the first groups of the device. In this case, the sampling signal arrives at the second input of the AND 33 element, and the address code does not yet finish the exchange of fo for the second information input of the circuit between the JM VA and the VM with a lower comparison of each switching priority (the VM priority is determined by the block 3 j-th row of the matrix. In addition to that is the sequence number, the higher the address code is received through the input number - the higher the priority). In response to the sign of the j-ro block 5 to the second inn, the request signal of the jth VA sends to J5 the formation input of the comparison circuit 64, the jth permission input of the first device in which the comparison signal does not occur j-ro of block 1 of the first group successively passes all

yes addresses with the register contains 63 characters. If, in the comparison circuit 23, the received add address is compared with the contents of register 63 of the feature. If in the comparison circuit 23, the received adigendal level from the output of the ciceMbi 23 comparison is compared through the OR element 27, it arrives at the first input of the AND element 33, the output signal of which is set to the trigger 29, the unit level from the direct output of which enters to the j-ro request input of block 2 of the second group and further from the output of the request of the second group of the device

switching blocks 3 of the j-th row of mat-pO rea with the contents of register 21, then the policers in each of them trigger state 28. If trigger 28, for example, in switching block 3 located at the intersection of i-ro column and j- the first row of the matrix is in the single state, then at the output of the element And 31 a single level is formed, which, having passed through the element OR 26, opens the elements AND of groups 24 and 25 to exchange space data as a request signal from the i-th VM and JM BA. In addition, there is the i-th VM. In the case of incomparison, the ad-signal from the output of the element of stresses or when comparing them, but with the i-ro block ready input, there is a zero level, in the second 2 second group and then from the output of the input element I 33, trigger 29 In the second group of devices, a single state is not set up in the i-th VM as a ready-to-use signal. This eliminates the possibility of tee, according to which the j-VM starts intercepting the i-th VM by an external subscriber for data exchange with J-M VA. If the trigger 28 with a higher priority before the request windows is in the zero state of the exchange already started between the i th scientific research institute, then at the output of the AND 34 for- 40 VM element and the external subscriber with a lower one, a single level which priority VA is defined — the total inversion in the element is NOT 36 by its serial number: what

the higher the number, the higher the priority).

In response to the request signal of the i-th VM, to the second control input of the mouth, the enable signal, which is

request for the i-th block 2 of the second group

sequentially passes all switching units 3 i-ro matrix columns.

closes the AND 32 element. In addition, the output signal of the AND 34, as a resolution signal, is fed to the second inputs of the AND elements 31 and 34 of the next switching unit 3 of the jth row of the matrix. The signals at the inputs of the sample, request, resolution, and readiness remain during the entire time of each of them interrogating the exchange status until the i-VM of the request trigger 29. If last,

for example, in the switching unit 2, located at the intersection of the i-th column and the j-th row of the matrix, is in the single State, then at the output of the AND 30 element a single level is formed, which, having passed through

does not remove the sampling signal, which results in the removal of the remaining control signals. In the case of accessing the jth VA of several VMs at the same time due to the sequential passage of the resolution signal, the data exchange, for example, between JM VA and the jth VM, is started by issuing the address of the jth VM to JM VA and the control signal of the sample, respectively, to the inputs of the data address and the sample of the first groups of the device. In this case, the sampling signal arrives at the second input of the AND element 33, and the address code goes to the second information input of the comparison circuit 23 of each switching unit 3 of the jth row of the matrix. In addition, the address code enters through the sign input of the j-ro block 5 to the second information input of the comparison circuit 64, in which no comparison is made

yes addresses with the register contains 63 characters. If in the comparison circuit 23, the received adigendal level from the output of the ciceMbi 23 comparison is compared through the OR element 27, it arrives at the first input of the AND element 33, the output signal of which is set to the trigger 29, the unit level from the direct output of which enters to the j-ro request input of block 2 of the second group and further from the output of the request of the second group of the device

If you go with the contents of register 21, then the i-th VM is issued as a request signal. In the case of the incomparison of the addresses or when comparing them, but in the presence of a zero level, the second input of the element 33 does not set the trigger 29 into a single state. This eliminates the possibility of intercepting the i-th VM by an external subscriber with a higher priority before the end of the already started exchange between the i-th 0 VM and an external subscriber with a lower priority (the VA priority is determined by its sequence number:

sequentially passes all switching units 3 i-ro matrix columns.

interrogating in each of them the state of the trigger 29 of the request. If last,

their subsequent connection to the jth VA.

element OR 26, opens elements AND groups 24 and 25 for switching the flow

data forks between the jth VA and the i-th VM. In addition, the signal from the output of the element 30 is fed to the ready input of the j-th unit 1 of the first group and then from the output of the device's ready output is issued to the j-th VA as a ready signal, through which the j-th VA starts data exchange with the i-th VM. If the trigger 28 of the query is in the zero state, then

the output of the element 35 is formed by the single-counting meters 55, which begins with a reasonable level, which, after inverting the element 39, closes the element 33 and 33. In addition, the output signal of the element 35 as an enable signal goes to the second inputs of the elements 30 and 35 of the next switching unit 3 i-ro matrix columns. At the end of the exchange, j-and-VA removes the sampling signal, which results in the removal of the remaining control signals. In the case of accessing the i-th VM of several VA simultaneously, due to a sequential passage of the resolution signal, they are connected in series to the i-th VM.

In the exchange mode without an address initiated by external subscribers, a data record, for example, a j-ro BA in a VM accessible to it, in the input buffer memory of which there are 30 remaining in delay element 62 delays the smallest number of occupied pulse positions to the counting-counting subtracting inputs It starts with the j-kov 55. If among the compared numbers by the external subscriber of the feature code and there are at the same time several control signal of the corresponding minimum sample, then, asynchronously, at the inputs of the data address and deduction their counterparts .55 become only one trigger 56 in a single state, which eliminates ambiguity when choosing a computer for exchange. Thus, 40 unit output signal of the K-th flip-flop 56, indicating that K-a VM is selected for exchange with the i-th VA, goes to the K-th output 67 of the block 5 and further to the second input, the OR element is carried out Comparison of the post 5 5 switching unit 3, which placed the code with the contents of the register. At the intersection of the j-th line 63 of the sign. As a result of the comparison and the K-th column of the matrix. The unit output of the circuit 64 comparing a form-level from the output of the element OR 27 to, - is a level difference from zero to one at the first input of the element AND 33, which is, affecting the inputs 50 by the output signal of which the synchronization of the counters 55, is performed in a single state, the census of the contents of the Herz 29 counters is triggered. Next, the operation of the device is similar to the work in the exchange mode at the address initiated by BA. After removing the comparison circuit 64, arriving at the first VA from the information input, the input input (N + T) -ro of the element 59, the sign code on the output of the circuit, decides the passage of the generation-64 comparison pulses j ro block 5 is formed

level difference from one to zero, which triggers the one-shot

Borki first group of the device. In this case, the sampling signal arrives at the second input of the AND element 33, and the code of the feature arrives at the second information input of the comparison circuit 23 of each switching unit 3 of the jth row of the matrix. In addition, the code of the feature goes through the input of the feature j-ro of block 5 to the second input 64 of the comparison, in ko4 to the corresponding counters 55. In addition, the unit level from the output

torus 61 through the element 62 of the delay on the first inputs of the remaining elements And

59. Since only those elements, AND 59, are opened, the second inputs of which are supplied with a single level from availability register 60, the pulses then go to the subtractive inputs of those meters 55 whose sequence numbers are the same as VM numbers available for j-ro WA. Under the influence of state pulses, a subtracting counter is computed, for example, with the sequence number K in which the minimum number is written, before other subtractive counters go from the 00 ... O state to the 11 ... 1 state, as a result which, at the output of its higher bit, forms a voltage level difference, which, I affect the counting input of the K-th

trigger 56-, sets it to a single state. At the same time zero: the level from the inverse output of the K-th trigger 56 through the element And 58 enters the second input of the element And 59,

prohibits further passage of the pulses of the generator 61 to the input of the element; that 62 delays. The same level, entering the third entrances of the elements of AND 59 group, prevents the passage

57, the output pulse of which sets the triggers 56 to the zero state, thereby preparing the jth block 5 for the next cycle of operation.

When installed simultaneously in unit state of triggers 28 and 29 in the switching unit 3. Located, for example, at the intersection of the j-th column and the j-th row of the matrix, the preference is about setting the switching on the initiative of the i-th VM. In this case, the jth HA removes the sampling signal, which leads to resetting the trigger state to zero. At the same time,

The data, resolution and sampling inputs of the first and second groups of the device, the outputs of the data, request and readiness of the first and second jrpynn bus driver blocks are the corresponding inputs

W

data, request and readiness of the first and second groups of the device, outputs of the data address and sample j-ro (j 1, M) of the bus drivers unit of the first group are connected to the first inputs of the data address and sample of the j-group switching blocks, outputs the address of the request signal received at the input) 5 data and sampling i-ro (i 1, N) of the j-ro block of block 1 of the first group, bus drivers of the second group of the j-th VA, gives the enable signal, which in the switch module 3, located at the intersection of the i-ro column and the j-th row Ritsa opens the elements 20 and groups 24 and 25 for switching of data streams between the i-th BM and J-M BA.

Thus, the proposed device for interfacing has wider functional capabilities than the known one, since when writing data to computers, at the initiative of external subscribers it provides a choice of computer to enable (i-1) -th switching input as address, as well as the minimum block of the same group, the second load of the input buffer memory devices. The choice of the mode — exchange by address or without address — handles the external subscriber by sending information lines of either the address code of the computer or the code of the feature. Expanding the functionality of the device entails an increase in the bandwidth of 40 computing system

The plugs are connected respectively to the second inputs of the data address and the sample ix of the switching blocks of all groups, the output of the j-ro block of the bus drivers of the first group is connected to the first input of the resolution of the N th of the switching block of the j-th group, the output of the resolution of the 1st block of bus shapes 25 worlds of the second group are connected to the second input of the resolution of the i-ro switching unit of the M-th group, the first output of the resolution of the i-ro switching unit of the j-th group is connected to the first

the resolution enable path of the 1st switching unit of the jth group is connected to the second enable input of the i-ro commutator

35 blocks (j-1) -th group, the first outputs of readiness, interrogation and data of the switching blocks of the j-th group are connected, respectively, to the inputs of readiness AND | request and data j-ro block bus drivers of the first group, the second outputs ready, request and data i-x switching blocks of all groups are connected respectively to the inputs ready, request and data i-ro

machines, because external subscriber messages are more evenly distributed between computers due to the analysis of the buffer storage devices.

Claims (3)

1. A switching device, with the selection of the least loaded subscriber, The device contains N counters and Мбло-Хов to determine the minimum number, with the inputs of positive and negative increments of the i-ro counter holding two groups of blocks of bus formers and M groups of N commuting blocks (where M is the number of blocks of bus formers. first group. N - the number of bus formers blocks 55 are connected respectively to the outputs lei of the second group), and the inputs of the address of the data, the resolution and the sampling of the blocks of bus drivers of the first and second groups are correspondingly. the occupation signal and the i-ro release signal of the bus group of the second group of drivers, the occupation and mastering inputs of which are the i-th input inputs of the data address, resolution and sample, respectively, of the first and second device groups, data outputs, request and readiness of the bus blocks the shapers of the first and second jrpynn are corresponding to you five W )50 data, request and readiness of the first and second groups of the device, outputs of the data address and sample j-ro (j 1, M) of the bus drivers unit of the first group are connected to the first inputs of the data address and sample of the j-group switching blocks, outputs addresses) 5 data and samples i-ro (i 1, N) of block shapers of the second group 0 0 to the enable input of the (i-1) -th switching unit of the same group, the second one is 0 The plugs are connected respectively to the second inputs of the data address and the sample ix of the switching blocks of all groups, the output of the j-ro block of the bus drivers of the first group is connected to the first input of the resolution of the N-ro switching block of the j-th group, 5 worlds of the second group are connected to the second input of the resolution of the i-ro switching unit of the M-th group, the first output of the resolution of the i-ro switching unit of the j-th group is connected to the first the resolution input of the (i-1) -th switching unit of the same group, the second the resolution enable path of the 1st switching unit of the jth group is connected to the second enable input of the i-ro commutator of the block (j-1) -th group, the first outputs of readiness, request and data of the switching blocks of the j-th group are connected, respectively, to the inputs of readiness AND | request and data j-ro block bus drivers of the first group, the second outputs ready, request and data i-x switching blocks of all groups are connected respectively to the inputs ready, request and data i-ro block bus drivers of the second group, characterized in that, in order to increase the capacity of the device and expand it the occupation signal and the i-ro release signal of the bus group of the second group of drivers, the occupation and release inputs of which are the i-th input 12128548610 In order to capture and release a device element NOT, the third input, the output of the i-ro counter is connected to the element NOT connected to the output of the fifth to the i-th information input of all AND elements, which is the first unit for determining the minimum number of the switching enable a, the input of the j-ro attribute of the block, the input of the fourth element is NOT the minimum number connected connected to the output of the sixth element to the output address of the bus AND block, which is the second output of the first shaper of the i-th resolution switch block, pr - request control output j-ro block outputs of the first and second trigger- determining the minimum number of plots are connected to the first inputs corresponding to the request control output of the second and first elements of the i-ro switching block j- th group. comrade and u are the first and second 2. The device according to Claim 1, of which the output of the request of the switching unit is that the switching unit, respectively, the inverse outputs of the unit, contains two registers, two circuits of the 15th and second triggers are connected, two groups of elements I, to the first inputs of the fifth and sixth ele- ral two elements IL, two triggers, six cops And, respectively, the second inputs of the elements I and four elements NOT, the second and fifth elements And a sub-and the outputs of the first and second lines to the first input of the resolution of the computers are connected to the first information iruyuschego block per- second inputs, the inputs of insulating the first and second circuits Vågå and sixth elements and are connected comparisons, respectively, the second information jK to the second resolution input, the commutation inputs of which of the connecting unit, the outputs of the first and second inputs to the first inputs of the corresponding groups of elements I are the corresponding elements of the first and second groups 25 respectively, and are the second of these switching units, the first inputs of the address of the switching 3. The device according to claim 1, 1 and 2 of the corresponding block, respectively, is the second so that the block determines the inputs of the elements of the first and second and the minimum number contains K groups connected to the output of the first 30 counters, N triggers, single vibrator, the OR element, the first and second inputs of the multi-input element AND, (N + 1) three of which are connected respectively to the input elements AND, the register is accessible to the outputs of the first and second elements, the pulse generator, the element AND, which are respectively, the delay, the register of the sign and the scheme of the first and second the readiness outputs 5 are compared, and the information input of the switching unit, the outputs of the first i-ro counter (i 1, N) are the i-th and the second comparison circuits are connected to the information input of the block determined by the first inputs respectively of the third minimum number, the output is old - its element AND the second element OR, whose bit is the i-ro counter. Connected is the second input of which is input 40 to the counting input of the i-trigger, the control inputs of the request of the switching unit to zero of the triggers are connected to the first at the same time Rathore, whose input is the input of the fourth AND gate, outputs connected to inputs sinhronyzatssh sche- third and fourth AND element and to the output tchikov .sravneni circuit .Connect inputs to install in units of first data input 45 which . One and the second, respectively, is connected to the output of the register of the sign, flip-flops, the installation inputs are zero and the second is the input of the sign — the second ones are connected to the outputs of the first minimum definition block and the second elements are NOT the first input i-ro (i 1, N) is three-way, the input of the first element is NOT connected to the input element AND is connected to the calculator to the second input of the third element of the i-ro register bit available AND, and is the second input of the sample, the first input (N +1) -ro three-input switching unit, the input of the second element And connected to the input of the element is NOT connected to the second input of the single-oscillator, the direct output of the i-th fourth element I and is the trigger is the ith output control input sample of the switching laziness request of the mic block, the third inputs of the third and an even number, the inverse output of the elements I are connected And the corresponding i-ro trigger is connected to the i-th input BSTCTBieHHo to the codes of the third and four-input I elements, the output of the 11 1 285486 12 the third input to the output (N + 1) -ro of the three-input element (i T7N) of the three-input element And, the third input of which is connected And connected to the i The output to the element is the output of the pulse generator. 54f 53 Fie.2 Fig.Z