SU1608681A1 - Device for connecting subscribers to computer trunk line - Google Patents

Abstract

The invention relates to computer technology, in particular, to devices for interfacing various peripheral devices with computer mains. The invention can be used in interface devices of computer complexes. The aim of the invention is to reduce hardware costs and expand the functionality of the device by programmatically setting addresses. The goal is achieved in that the device contains two main transceiver units, a control signal decoding unit, an interrupt vector address register, an address register, an interrupt unit, two triggers, two OR elements, and a multiplexer. 3 il.

Description

The invention relates to a computational technique, in particular to the means of interfacing various devices with a computer mainline, and can be used in interface devices of computer complexes based on MINN and microcomputers.

The purpose of the invention is to reduce hardware costs and expand functionality by programmatically setting addresses.

On ig. 1 shows the block diagram of the device: TWA; 2 and 3 are functional diagrams of the decoding unit of control signals and the interrupt unit, respectively.

. Setup :-) The device contains (FIG. 1) the first bl 1 of trunk transceivers (address data bus), the second block 2 of trunk transceivers (control plane), block 3

decoding control signals, address register 4, interrupt vector address register 5, interrupt block 6, triggers 7 and 8, OR elements 9 and 10, multiplexer 11.

The control signal decoding unit 3 contains (FIG. 2) an element, 12 comparisons, a register 13, a trigger 14, an element NOT 15, elements AND 16 and 17, an element OR 18, decoders 19 and 20.

The BLOCK 6 offsets contains (fig.Z) the element OR 21, the triggers 22 and 23, the elements AND 24 and 25.

The diagrams also show the data address busses 26 and the computer control bus lines 27, the input buses 28 and the output buses 29 connected to the information outputs and inputs of external device registers, the output lines 30 and 31 of the sample registers of subscribers (external devices) during recording and

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reading, as well as lines 32-43 of internal communications between the units of the device.

The device (adapter) works in the following way.

The main control reset signal received by block 2 returns to its initial state register 4, triggers 7 and 8, block 6. In this case, register 4 is set to the state corresponding to the starting address of the adapter, trigger 7 to the state Log. O, the trigger 8 is in the state of Log.1, the initial state of the block 6 is the absence of interrupt request signals, output, addresses of the interrupt vector, interrupt resolution.

At the moment of time determined by the program being executed, the computer starts distributing addresses to the adapters. This happens in the following way. The computer sets the starting address of the adapter on the data address bus 26 and accompanies it with a control signal for synchronization of exchange in line 35. The address set on bus 26 is received in each adapter by block 1 and from its outputs goes to a group of information inputs of block 3, on another group of information the inputs of which there is the initial address of the adapter, coming from the outputs of the register 4.

In block 3, both addresses are compared by element 12, at the output of which, due to the absence of the inhibit signal, a coincidence signal appears at the information input of the trigger 14.

The control signal for synchronization of exchange is received in each adapter by block 2 and via line 35 goes to the same input of block 3.

In block 3, the synchronization signal of the exchange arrives at the synchronous inputs of register 13 and trigger 14, fixing the address of the address at their outputs and coinciding with the address of the adapter, respectively, until the end of the operation on the highway.

The computer removes from the bus 26 the starting address from the adapter (if the operation occurs on the multiplexed bus). The computer sets data on bus 26, which, according to the program, is the address of the interrupt vector, and accompanies them with a controlled write synchronization signal. The data set on bus 26 is taken in

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each adapter by block 1 and from its outputs are fed to the information inputs of register 5, the control write synchronization signal is received in each adapter by block 2 and via line 36 to the same input of block 3.

In block 3, the write synchronization signal through element 16 enters the input of element 18, providing a signal at the response output 32 of block 3, and also entering the enable input of the decoder 19, providing a signal at one of the write control outputs 30 of block 3 corresponding to register 4 or register 5.

The signals at the specified output of block 3 sets the trigger 7, ensuring that the address of the interrupt vector is written to register 5, as well as the occurrence of a signal at input 41 of the interrupt request of block 6.

In block 6, the occurrence of the interrupt request signal line 41 sets the trigger 22, which triggers the interrupt request signal of the block 6 on line 37.

The interrupt request signal from the output of block 6 goes through line 37 to the input of block 3 and further to the corresponding bus line 27. In addition, the interrupt request signal from the output of block 6 goes to the inhibit input of block 3. In block 3, the inhibit signal goes through element 15 input permission element 12, prohibiting the comparison operation, and hence the issuance of a coincidence signal element 12.

The response signal on line 32 through element 9 is fed through block 2 to the bus line of the same name 27. After the response signal appears, the computer removes the write synchronization control signal from the bus 27. Removing the write synchronization signal leads to the removal of signals on line 32 and the output of the recording control unit 3, and therefore to the removal of the response signal on bus 27 and the removal of the signal on the trigger input 7, after removing the response signal of the computer removes data from the bus 26, and then the control signal synchronization exchange on the bus 27.

The removal of the exchange synchronization signal on the bus results in the removal of the signal of the same name on line 35 and unlock the register 13 and the trigger 14.

the presence in line 37 of the request signal from block 6, and following, the prohibition on the input of block 3, prohibits the prohibition of the part of the adaptation operations of address exchange until the address is read

The interrupt request set by the highest-priority version is first. Computer set

bus 27, the synchronization signal, and then the enable signal. These signals are received by block 2 adapters with a higher

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Hct of this address exchange with the operation of recording the address of the interrupt vector L of each adapter ends.

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those mountains, until the address of the interrupt vector in the given adapter is read.

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The ynpai input of multiplexer 11, the KOTOI switch the outputs of register 5 to the information inputs of the block. In addition, the specified signal through element 10 enters the input of the transmission resolution of block 1, providing the addresses of the interrupt vector of the record; this is in register 5 on the information lines 26. The signal from line 3.9 through element 9 also arrives

43 to the inputs of block 6. block 6, the trigger signal is set by the synchronization signal 23. The woven trigger 23 blocks element 25 and allows the signal to pass from line 43 to the output line of the address of the vector interrupt, and also provides a reset 22 through element 21 and interrupts the interrupt 37. Pine from exit 39 enters

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A block 2 input is provided to provide: a response signal on the corresponding bus line 27, and a reset trigger 8.

Pseudo-occurrences of the response signal on the PCs do not 27 computers remove the signals for the sync read and enable, interrupt on the control bus, which causes the interrupt vector signal of block 6 in the adapter, the interrupt of which is interrupted, and the response signal to be removed from line 39. bus adapter 27.

The interrupt service routine includes address exchange with the write operation of the adapter's own address.

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The computer is installed; - the initial address of the adapter fits on the bus 26 and is accompanied by its control signal for synchronization of the exchange. The address established on bus 26 is received in each adapter by block 1 and from the outputs of the indicated block is fed via bus 29 to a group of information inputs of block 3, on the second group of information inputs of which the initial address of the adapter is present.

Since, in all adapters, in addition, the address of the interrupt vector of which is read, the operation of block 3 is prohibited, then the coincidence of addresses and the address itself will be recorded only in this adapter.

The computer sets data on bus 26, which, according to the program, is its own adapter address, and accompanies them with a control write synchronization signal. The set data is received by block 1 and via bus 29 is fed to the information inputs of register 4. The control write synchronization signal is received by block 2 and via line 36 is fed to the input of block 3.

In adapter block 3, the interruption of which is serviced, a signal is output on line 32 and one of the write control outputs 39 corresponding to a register 4 or 5.

The signal at the specified write control output of block 3 sets the trigger 8, ensuring that the adapter's own address is written to register 4. The response signal is generated in the same way as when writing the address of the interrupt vector.

After the response of the computer appears, the recording timing control signal is removed, which results in the removal of signals on lines 32 and the output 30 of the recording control unit 3, a. therefore, to the removal of the response signal on the bus 27.

After the response of the computer is removed, the data is removed from the data address bus 26, and then controlled; the synchronization signal is exchanged from the bus 27 In the same way, interrupt requests caused by adapters with lower priorities are serviced

After completing the distribution of addresses, each adapter provides address exchange operations with the main line of computer registers connected to the adapter. At the same time, the information outputs of the adapter are connected to the information inputs of the registers, the outputs for controlling the recording of the adapter are connected to the synchronous inputs of the registers, the outputs for controlling the adapter's tag are connected to the inputs of the registers, providing information of the registers to the information inputs of the adapter.

The write operation to the register connected to the adapter is performed as follows; the computer sets the address of the register connected to the adapter on the data address bus 26, accompanied by its exchange synchronization signal on the control bus 27. The address set on bus 26 is received by block 1 and via bus 29 goes to the first group of information inputs of block 3, on the second group of information inputs of which there is an adapter address coming from the outputs of register 4. In the block both addresses are compared by element 12 whose output is if the register address belongs to the adapter's address area, a match signal appears, arriving at the information input of register 13, the exchange synchronization signal is received by block 2 and on line 35 enters the input of block 3. In block 3, the syn exchange ronizatsii supplied to the clock register 13 and the latch 14 fixed at their outputs, and register address coincidence signal (or mismatch) to the end of performing operations on the line.

The computer removes the register address from the bus 26 (if the operation takes place on the multiplexed bus), sets the data and accompanies it with a write synchronization signal on the control bus. The data installed on bus 26 is received by block 1 and received via bus 29 to the information inputs of the registers connected: x to the adapter. The write synchronization signal is received by block 2 and on line 36 enters the input of block 3. In block 3, if there is a coincidence signal at the output of trigger 14, the write synchronization signal through element 16 enters the input of element 18, providing a signal at the response output of block 3, as well as enters the enable input of the decoder 19, providing a signal at one of the control outputs 30 for

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record according to the address of the register on the information inputs of the decoder 19. The signal from the response output of block 3 through element 9 and block 2 is fed to the bus 27 and the output of the specified block. The signal from output 30 is fed to the sync input of the register connected to the adapter, ensuring that data is written to the selected register. After the response signal appears on bus 27, the computer removes the write synchronization signal, which leads to the removal of the signal on line 32 and bus 27. After removing the response signal on the computer line 32, it removes data from bus 26, and then the synchronization signal from bus 27 .

The computer removes the register address from the bus 26 (if the operation takes place on a non-multiplexed bus). This completes the write operation to the register connected to the adapter.

The read operation of the register connected to the adapter is as follows. The computer sets on bus 26 the address of the register connected to the adapter, accompanied by its exchange synchronization signal on bus 27 in the same way as was done in the write operation. Similarly, the exchange synchronization signal on line 35 captures the register address and the match (or mismatch) signal at the outputs of register 13 and trigger 14. The computer removes the register address from the bus 26 (if the operation occurs on the multiplexed bus) and sets the read synchronization signal received by the adapter unit 2 on the bus 27. The read synchronization signal on line 34 enters the input of block 3, where, if there is a coincidence signal at the output of trigger 14, the read synchronization signal through element 17 enters output 3 of the adapter and 18 through element 18 on line 32. The signal from line 34 also enters the enable input decoder 20, ensuring the formation of a signal at one of the outputs 3 of the read control unit 3 for reading the corresponding register of the external device.

The signal from line 33 through element 10 enters the transmission enable input of unit 1, providing, via multiplexer 11, switching buses 28 for information outputs of a selected external device register to information inputs / outputs for the signal. Signal

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From line 3. through e; dark-1-9 and block 2 arrives at the response line of bus 27. When a splendid signal appears on the computer horn 27, it reads the read synchronization signal, which leads to the removal of the signal from the bus 26 and the response signal from bus 27, After removing the response ct, the MBA removes the synchronization signal of the exchange.

The computer removes the afpec register from the address-data bus (if the operation occurs on a non-multiplexed bus).

This completes the reading of the register of the external device connected to the adapter.

f | formula of invention

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I A device for connecting subscribers to a computer trunk, which contains the first and second main blocks with e transceivers, the input-output groups of which are, respectively, the input-output groups of the device E1 connected to information and communication lines of the computer mainline, and the Output groups are connected correspondingly with the first group of informational and group of control inputs block for decoding the control signals, the address register connected by the group of information inputs with the group of outputs of the first trunk block The group of information inputs of which are connected to the group of outputs of the multiplexer, the first group of information inputs connected to the group of outputs of the register of the address of the interrupt vector of the vector, two triggers, two elements of the IL and the interrupt block, the input of the resolution and the first input of which are connected respectively to the first output and input resolution of the second block of main transceivers, about t l. and h

e in order that, in order to reduce the hardware costs of the device, the group of information inputs of the register of the address of the pre-Shani vector is connected to the group of outputs of the first block

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the main gateway drivers and the sync input are equipped with a trigger for the first trigger and input npepi-interrupt demand inputs, a synchronization input, a reset output and a BTOpofi output which are connected respectively to the output group, the second output and the output of the interrupt inhibit signal of the second trunk unit transceivers connected by the input of the response signal to the output of the first HJIII element, the first output of which is connected to the first output of the decryption block of control signals, and the second input to the third output of the interrupt block, the multiplexer input, the reset input of the second trigger and the first input of the second HJTO element, the output and the second input connected respectively to the enable input of the first block of main transceivers and the second output of the decryption control signals, the second group of information inputs and the prohibition input of which are connected respectively the group of outputs of the address register and the second output of the interrupt block, and the first and second groups of outputs are the corresponding groups of outputs of the device for connection to the group the memory of address inputs for recording and reading subscribers; the synchronization input of the address register is connected to the output of the second trigger, and the installation input to the second output of the second block of trunk transceivers and the installation inputs of the first and second triggers, the information inputs of which are connected to the logic unit, and the synchronous inputs to the corresponding output of the first group, the outputs of the decoding unit of control signals, the second group of information inputs of the multiplexer and the group of outputs of the first trunk unit, transceivers The circuits are the corresponding groups of inputs and outputs of the device for connecting to the groups of information outputs and subscriber inputs.

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Claims (1)

A device for connecting a subscriber, containing the first and second blocks of the main transceivers, the input-output groups of which are respectively the input-output groups of the device for connecting to the information and dimming buses of the computer main, a. groups of outputs are connected respectively to the first group of information and the group of control inputs of the control signal decryption unit, an address register connected by the group of information inputs to the group of outputs of the first block of main transceivers, the group of information inputs of which are connected to the group of outputs of the multiplexer, trans, permission input and the first to the entire group of information inputs of the address of the trigger interrupt vector connected to the group of outputs of the register, two OR elements and an interrupt block whose output are connected respectively to the first output and the permission input of the second block of trunk πρι Щ 'щ! gr: RA on emitters, about t l. And moreover, in order to save the hardware costs of the device, the UPA of the information inputs of the register of the interrupt vector is connected by the group of outputs of the first block of the main transceivers, and the sync input is connected to the output of the first trigger and the interrupt block input of the interrupt block, synchronizing 5 input, the reset input and the second output of which are connected respectively to the group of outputs, the second output and the input of the interrupt inhibit signal of the second block of trunk transceivers, connected by the input of the response signal to the output of the first OR element, the first output of which is connected to the first output of the decryption unit 15 control signals, and the second input to the third output of the interrupt unit, the control input of the multiplexer, the reset input of the second trigger and the first input of the second OR element, output 20 and the second input connected respectively to the enable input of the first block of main transceivers and the second output of the control signal decryption unit, second Paradise 25, the group of information inputs and the prohibition input of which are connected respectively to the group of outputs of the address register and the second output of the interrupt unit, and the first and second groups of outputs 30 are the corresponding output groups of the device for connecting to the groups of address inputs for recording and reading subscribers, the sync input of the address register is connected to the output of the second trigger, and the installation input with the second output of the second block of trunk transceivers and installation inputs of the first and second triggers, information inputs 4Q of them are connected to the logical unit bus, and the clock inputs - with the corresponding output of the first group, outputs of the control signal decryption unit, the second group of information 45 inputs of the multiplexer and the group of outputs of the first block of trunk, transceivers are the corresponding groups of inputs and outputs of the device for connecting to groups of information outputs and subscriber inputs.