SU1518893A1 - Device for measuring error factor - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to expand the range of velocities of the measured error streams. The device contains an error selection block 1, counting decades 2 ₁ - 2 _to the upper counting control unit 3, a control unit (CU) 4, a 5 degree indicator, a 6 number indicator, a 7 error counter, a counting generator 8, counting key 9 a decoder of 10 reciprocals, blocks 11–13 of memory, a counter of degree 12, and an overflow indicator 14. During the counting process, consecutive filling of decades 2 ₁ - 2 _k occurs. The "overflow" signal from the output of the control unit 3 is fixed by indicator 14 and indicates that the measured error rate is less than a predetermined value. The errors coming from the allocation unit 1 are counted by the counter 7, the signal of which closes the key 9 and the filling of the decades 2 ₁ - 2 _{k is} stopped. The number of pulses counted decades 2 ₁ - ₂ for the filling of the counter 7 is numerically equal to the average interval between errors i.e. the reciprocal of the error rate. The reflection of the number and degree of error ratio is carried out by indicators 6 and 5. The goal is achieved by the introduction of control block 3, memory blocks 11 and 13, counter 12 and indicator 14. The device according to claim 2 is different in performance of control unit 4. 1 Cp. -l, 2 il.

Description

ate

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with so

WRITTEN

1

counters, return code decoder 10, memory blocks 11 and 13, 12 degree counter and overflow indicator 14. During the counting process, successive filling of decades 2, -2 | occurs. The overflow signal from the output of control unit 3 is fixed by indicator 14 and indicates that the measured error rate is less than the specified value. Errors coming from the allocation unit r1 are counted by the counter 7, the signal of which closes the key 9 and the filling of the decade 2, | -2 |

The invention relates to telecommunications and can be used in control devices for 1-information transmission systems.

The purpose of the invention is to expand the range of velocities of the measured error streams.

Fig. 1 shows a structural electrical circuit of the device proposed; Fig. 2 is a structural electrical circuit of the control unit.

The device for measuring the error rate contains a block 1 - NIN error, counting decades., Block 3 controls the higher counting decade, control block 4, 5 degree indicator, 6 number indicator, 7 error counter, counting pulse generator 8, resolution key counting, the decoder 10 return values, the first memory block 11, the counter 12 degrees, the second memory block 13 and the overflow indicator 14, and the control block 4 includes a setting signature switching block 15, a shift register 16, a reset signal generator 17 , switch 18 slave mode You and former 19 counting pulses.

The device works as follows

The initial state is set by the reset signal from the control unit 4 at the end of the next counting cycle in the automatic mode, or when input is sent to the Reset-start input of the control unit 4 of the corresponding signal in the manual measurement mode. Under the action of the reset signal, the counting decade 2, counter 7 Oyibok and the generator 8 counting pulses are set to 1BL1oot to the original zero stop. The number of pulses calculated in decades during the filling of counter 7 is numerically equal to the average interval of the method with errors, t, e, the reciprocal of the error rate. The reflection of the number and degree of error ratio is carried out by indicators 6 and 5. The goal is achieved by the introduction of control block 3, memory blocks II and 13, counter 12 and indicator 14. The device according to claim 2 differs in execution of CU 4, 1 hp, f -l, 2 il,

new state. A counter of degree 12 is set to the state k, e, equal to the number of counting decades. Simultaneously with the Reset signal, signals are present at the outputs of the installation of the control unit 4 that allow the rest of the counting decades 2 to be set to the zero state,

At the end of the signal Reset signals at the outputs of the installation of block 4 take the values that prohibit the installation, and the counting begins. The signal from the output of the generator 8 counting pulses through the key 9 resolution resolution is fed to the counting input of the youngest counting decade 2, the frequency of the counting pulses is selected less than the speed of information in the measured canile in the number of times equal to the capacitance counter 7 errors,

During the counting process, the counting decade 2 is successively filled. If the k-counting decade begins to fill up during the counting process, this is recognized as an overflow of the counting decade 2 line, which can be signaled by the Overflow signal removed from the output of the control unit 3 of the upper counting unit. decades, t, e, signal occurrence An overflow in the counting process indicates that the measured error rate is smaller.

The errors received from the output of the error extraction block 1 are counted by the error counter 7, and at the moment it is filled, the output of the counter ends at the output of the counter 7, which is fed to the input of the account resolution key 9 and to the input of the control unit 4. Key 9 closes and zl5 .1

the completion of counting decades 2 is terminated.

The states of the output signals of the control unit 4 change under the action of the control clock frequency depending on the value of the input signals. When the end of the signal signal is applied to the corresponding inputs of control unit 4, provided that the highest counting decade 2 is not filled (i.e., it is in the O state), control unit 4 begins to generate a set signal sequence in such a way that the data in the lower counting decade 2 is moved to the higher ones until the value of the higher counting decade 2 (becomes different from zero. The shift in the data line of the counting decade 2 is as follows.

When the installation signal is applied to the installation input of any counting decade 2, its state becomes equal to the state of the previous counting decade 2, since the data inputs of all subsequent counting decades 2 are connected to the data outputs of previous counting decades 2, If the state of the older counting decade 21 corresponds to zero, then under the action of the control clock frequency, the installation enable signal appears at the corresponding output of the control unit 4, and the state of the k-th counting decade 2 becomes equal to the (and-1) -th counting deck s. At the same time, the signal from the output of control unit 4, which enters the input of the counter 12 of degree, the state of the counter 12 decreases by one and becomes (k-1). If the state of the senior counting decade 2, after the installation signal was given, did not change (remained zero), then the next clock at the outputs of control unit 4 will be the installation enable signals, according to which the values of the kth and (kl) th counting decades 2 becomes equal to the value of (k-2) -th counting decade 2; the state of the 12 degree counter decreases by one and becomes equal to (k-2). This process continues until the state of the group of the highest counting decades becomes equal to the state of the MPA and to it in the group other than zero. In this case, the state of the counter 12 degrees is equal to the number of this account 936

Noah of decade 2 and in the gallop is not in, In this case, the input resolution of the setting shadow of the decade decade 2 | A signal prohibits the installation from the corresponding output of control unit 4, and the installation inputs of the remaining counting decades 2 groups receive signals allowing installation, and the states of these counting decades 2 become equal to the state of the preceding group of counting decades 2. Then the process continues until the resolution installation of counting decades,

In this case, the state of these counting decades becomes equal to the state of the first counting decade 2,

In the k-M clock cycle of the control clock frequency from the moment the signal appears

The end of the counting at the output of the Record of control unit 4 generates with the enable signal the recording of measurement results in the first 11 and second 13 memory blocks. At the end of the signal

The recording measurement process is terminated. In the automatic measurement mode, the control unit 4 at the end of the signal. The recording generates the Reset signal and the counting is repeated, storing the previous measurement in blocks 11 and 13 of the memory.

In the manual mode, the repeated measurement is possible after a signal has been sent Reset-start to the corresponding input of the control unit 4. In this case, the control unit 4 generates a sequence of signals Reset and Record, after which the measurement begins.

Reflection of the number and degree of error rate on the corresponding in-- The speakers 6 and 5 are as follows.

Number of pulses counted

counting decades for filling the counter of 7 errors, is numerically equal to the average interval between errors, i.e., the reciprocal of the error coefficient, which can be displayed as

Koi A.10

s

where a

ten

Qt + Qk., / 10

S "k-l - the number of filled counting decades 2 (numerically equal to the counter of 12 degrees);

the value of the highest filled counting decade 2; the value of the penultimate filled counting deca hell 2;

total number of counting decades 2; number of blank account

decade 2 by the time

account termination

provided that Q | + Qk. (If equal to 1, A 9.9 is assumed,

The operating mode of the control unit 4 is determined by the state of the signals at the inputs of the operation mode switch 18. At the end of the count and the empty upper counting decade 2i, the corresponding signals arrive at the inputs of the operation mode switch 18. Only in this case, the output of the set resolution signal appears, which is sequentially recorded in the bits of the shift register 16

under the influence of the clock frequency of control, starting with the low-order bit k. When one of the input signals of the operation mode switch 18 is terminated, a signal appears on its output; a prohibitory setting, which is also sequentially recorded in the bits of the shift register 16. The signals from the outputs of the bits 2 - k of the shift register 16 through block 15 switch

arrive at the inputs of the installation, corresponding to 5, it writes to all the counting decades 2 data from the first counting decade 2, whose state is equal to zero (under the influence of the Reset signal).

frames 2 data from the first counting decade 2, whose state is equal to zero (under the influence of the Reset signal).

Note that by the time of the forming counting decades Z, under the action of these signals, data are sequentially overwritten from the younger counting decades 2 to the older ones before the older counting decade 2 is filled in (, 40 signals Reset in all bits When writing to the upper counting decade of the shift register 16 recorded signal

prohibiting installation.

Presetting the device for measuring the error ratio 45 is performed by the signal Reset2 nonzero data from the output of the control unit 3 of the higher counting decade to the corresponding input of the operating mode switch 18 a signal is received About filling} 1 and the leading counting decade 2 ,,

At the output of the operation mode switch 18, a setting inhibiting signal appears, which sequentially records a signal permitting the setting in one or several higher bits of the shift register 16.

Claims (1)

is written to the bits of the register. JQ. 1, A device for measuring the error rate, containing a generator of counting pulses, a control unit, a number indicator, a degree indicator and a series connected error extraction unit, an error count, a counting resolution key, the second input of which is connected to the output of the counting pulse generator, k 16 shift. Thus, the installation resolution signal is recorded in register 16 as many times (M) as there are unfilled higher counting decade 2 upon termination of the counting, i.e., e, the next bits of the shift register 15 are recorded with the installation resolution signal, which is sequentially shifted at 55 ten 15 20 five thirty side of the higher bits of the shift register 16 under the action of the control clock frequency. The shaper 19 of the counting pulses, under the action of the clock frequency of the control and the output signal of the lower bit k of the shift register 16, generates a sequence M of their pulses, which are fed to the counting input of the counter 12 degrees and reduce it, the state is on M, the Record Signal is removed from the output of the higher bit Yes 1 shift register 16 and corresponds to the setting signal, the dog that goes to the end of shift register 16. Signal duration Record is not constant and is equal to M - the number of unfilled counting decades 2 after the end of the count. The Recording signal is fed to the reset signal shaper 17, at the output of which, at the end of the Recording signal, a Reset signal is formed, under which a counter of degree 12 is installed, a fault counter 7, a counting pulse generator 8 and the first counting decade 2 are reset, In block 4 of the control signal, the Reset signal is supplied to the block 15 of switching the installation signal, on the outputs of which, by the action of the Reset signal, the installation signals are generated, which results in writing to all counting decades 2 data from the first counting decade 2, whose state is zero (due to the Reset signal). Note that by the time of the reset signal form, a signal is recorded in all bits of the shift register 16, a start that writes to one or more high bits of the shift register 16 a signal enabling the installation. .Record f ff f f „Reset - Start „Pl / HOU automatic removal -N J) HOH4aHue account 2.