SU1193784A1 - Device for generating pulse burst - Google Patents

Description

the third driver is connected to the inverse input of the unit to the unit of the third trigger, the inverse inputs of the unit to the unit of the second and fourth flip-flops are connected respectively to the outputs of the fourth and fifth shaper, the inputs of which are connected respectively to the third and fourth control buses, the output of the comparator is connected to the input first shaper.

2. The device according to claim 1 is that each driver contains an AND-NOT element and an odd number of series-connected NO elements, the input of the first and the output of the last of which are connected respectively to the first and second inputs of the AND-NOT element, the output of which connected to the output of the imager, the input of which is connected to the first input of the element.

. one .

The invention relates to digital technology and can be used to monitor computers with a pulse counting apparatus by sending a pack of any given number of pulses to a monitored device and then analyzing the state of the outputs of the monitored device.

A device for forming a bundle of 3. A number of pulses is known, comprising a pulse generator, a code comparison unit, a counter, logic elements for inhibiting the passage of pulses to the output of the device when the number of pulses counted by the counter is equal.

The disadvantage of this device is the relatively low functionality associated with the inability to form bursts of pulses with a single initial and / or / final level. Packs of pulses of this type are necessary to improve the diagnostic capabilities of the control device. This is an example, for which we consider a counter built on JK-flip-flops switching over a given front of the input signal. If a malfunction exists in one of the bits of such a counter, as a result of which the discharge does not jump to the falling edge of the input signal, but to the leading edge, then such a fault cannot be detected by using a device that forms a burst beginning and ending with a zero level, t . after the end of the last burst of a pack, it is impossible to determine from which front of the signal a switch of the controlled counter has switched.

A device for generating a burst of pulses is known, which contained a pulse generator, a single pulse generator, a trigger for the burst start, a binary counter, a comparison unit, an AND element, an AND-SHSh-NOT element, a forma- tion, five IS-NOT elements, a reset bus, and a group of tires, which is connected to the first group of inputs of the comparison unit, the second group of inputs of which is connected to the outputs of the binary counter, the output of the generator of a single pulse is connected to the clock input of the trigger of the pack start, the output of which is connected to the first input of the element And the output of which is connected to the control input of the binary counter, the output of the pulse generator is connected to the input of the imaging device, one of the outputs of which is connected to the clock input of the binary counter,

In the known device, logic elements serve to prohibit the cooling of the pulses from the pulse generator through the output element to the output of the device and zero the binary counter when it reaches the state specified by the external master unit.

A disadvantage of the known device is low functionality, due to the impossibility of forming pulse trains with unitary initial and / or / final levels. The purpose of the invention. The expansion of the functionality of the device. The goal is achieved by the fact that a pulse generator comprising a pulse generator, a single pulse generator, a pack trigger trigger, a binary counter, a comparison unit, the first AND element, the first OR element, the first driver, the NAND element, the reset bus and a group of master tires, which is connected to the first group of inputs of the comparator unit, the second group of inputs of which are connected to the outputs of a binary counter, the output of the generator of a single pulse is connected to the clock input of the pack trigger trigger, the direct output to first connected to the first input of the first element AND, four triggers are introduced, the second and third elements OR, the second, third, fourth and five drivers, the second, third and fourth elements AND four control buses and the holder element whose transistor is connected to the first inverse the installation input to zero of the first trigger, the second inverse input of the installation to zero of which is connected to the reset bus, to the inverse inputs of the installation to zero of the second, third, fourth triggers and to the first input of the NAND element, the second input of which is connected to the output m of the first driver, with the input of the delay element and with the inverse inputs of the second and third elements And, the direct inputs of which are connected respectively to the direct outputs of the second and fourth triggers, the outputs of the second and third elements And are connected respectively to the direct inputs of the installation to zero and one third of its trigger, the direct output of which is connected to the first input of the fourth AND element, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the first AND element and to the clock the input of a binary counter, the direct input of the installation to the zero of which is connected to the output of the NAND element, to the direct input of the installation to zero of the trigger of the launch of the 444, the inverse output of which is connected to the information input of the trigger of the pack start, the second input of the first element And is connected to the output of the pulse generator and with the first input of the generator of a single pulse, the second input of which is connected to the first control bus and to the input of the second driver, the output of which is connected to the inverse input of the unit into the unit of the first trigger, inverse The output of which is connected to the second input of the fourth element AND, the second and third control bus are connected respectively to the first and second inputs of the third OR element, the output of which through the third driver is connected to the inverse input of the unit of the third trigger, the inverse inputs of the unit of the second and fourth the flip-flops are connected respectively to the outputs of the fourth and fifth shapers, the inputs of which are connected respectively to the third and fourth control buses, the output of the comparator unit is connected to the input Odom first shaper. of the formers contains the element AND-NOT and an odd number of series-connected elements NOT, the input of the first and the output of the last of which are connected respectively to the first and second inputs of the element AND-NOT, the output of which is connected to the output of the driver, the input of which is connected to the first input of the element AND -NOT. The drawing shows a diagram of the device. The device comprises a pulse generator 1, a single pulse generator 2, a NAND element 3, a pack start trigger 4, an AND 5 element, a binary counter 6, a comparison block 7, a driver 8 containing HE 911 elements and an element AND-NO 12, driver 13, trigger 14, element 15, elements 16 and 17, elements 18 and 19, trigger 20, element 21, trigger 22, driver 23, trigger 24, element 25, delay element 26, a group of 27 master tires, 28 inu 28, control bus 29-32, output bus 33. A group 27 of master bus 1 is connected to the first group oh inputs of block 7 comparison, second group of inputs

which is connected to the outputs of the binary counter 6, the output of the generator 2 of a single pulse is connected to the clock input of the pack start trigger 4, the direct output of which is connected to the first input of the And 5 element, the output of the delay element 26 is connected to the first inverse input of the zero setting of the trigger 14, the second the inverted setup input to zero of which is connected to the reset bus 28, to the inverted inputs of the installation to zero of the flip-flops 20, 22 24 and to the first input of the 3 element AND-NOT, the second input of which is connected to the output of the rammer 8, to the input of the delay element 26 and from The top inputs of the And 21 and 25 direct inputs of which are connected respectively to the direct outputs of the flip-flops 20,24, the outputs of the Elements 21 and 25 are connected respectively to the direct inputs of the installation to zero and to the flip-flop unit 22, the direct output of which is connected to the first the input element AND 15, the output of which is connected to the first input of the element OR 16, the second input of which is connected to the output of the element AND 5 and to the clock input of the counter 6, the direct input of the setting to zero which is connected to the output of the element 3 AND-NOT, with the direct Trigger zero setting input, 4 starts Packs, the inverse output of which is connected to the information input of the trigger 4 packs, the second input element And 5 is connected to the output of the pulse generator 1 and the first input of the generator 2 of a single pulse, the second input of which is connected to the control bus 29 and the driver 13, the output of which connected to the inverse input of the unit into the unit of the trigger 14, the inverse output of which is connected to the second input of the element AND 15, the control buses 30 and 31 are connected respectively to the first and second inputs of the OR element 17, the output of which is formed Spruce 18 is connected to the inverse installation input to unit one trigger 22, the inverse inputs to installation one unit flip-flops 20 and 24 are connected respectively to the outputs of the formers 19 and 23, whose inputs are connected respectively to the control buses 31 and 32, the output of the comparator unit 7 is connected to the input of the former 8, the output bus 33 is connected to the output of the element OR 16.

In each of the formers 8, 5 13, 18, 19 and 23, the element ;, NOT 9-1 is connected in series, the input of the element is HE 9 and the output of the element is NOT 11 connected to the first and second inputs of the element AND-NOT 12,

0 the output of which is connected to the output of the imager, the input of which is connected to the first input of the element t-AND-12.

Code submitted by group 27.

5 tires, determines the number of pulses in a bundle and can be eadan, for example, from a toggle register or another driver. At the inputs of the installation to zero

0, the trigger 14 and the inputs of the set to zero and to the unit of the trigger 22, the OR function is implemented.

The device works as follows.

5 Generator 1 produces a continuous sequence of pulses that arrive at the inputs of the element 5 and the generator 2. In the initial state, all the triggers entering the device are reset by a bus signal28, therefore the pulse sequence does not pass through the element 5. It is positive. the front of the signal bus 29 trigger 14

is set to one, but in this case it does not affect the operation of the device, since the trigger 22 remains at zero. Generator 2 selects the closest, next to

by a signal on bus 29, a pulse of generator 1. On the falling edge of this pulse, trigger 4 of the pack is set to one and allows the pulse of generator 1 to pass through the device bus 33 through element 5 and element OR 16 and to the input of a binary counter 6.

The used generator 2 and trigger 4 allow to avoid passing the shortened pulse to the bus 33 of the device if the command on the bus 29 arrived at the time when the next generator pulse 2 was not finished yet, thus increasing the noise immunity of the device. The outputs of the binary counter 6 are connected bit by bit with one group of inputs of the comparison unit 7, to another group of inputs from which an external master unit or switch is supplied with a binary code corresponding to the required number of pulses in a burst. As soon as the number of pulses counted by counter 6 becomes equal to the number of pulses specified on tires 27, a unit potential appears at the output of the block, from which a negative pulse is formed using shaper 8, which initializes the triggers 4, 14 and counter 6 After zeroing of the trigger 4, the further passage of the pulses of the generator 1 through the element I, 5 to the input of the counter 6 and to the bus 33 of the device is prohibited. The burst of pulses at the output of the device has a zero level before and after the burst of pulses. If a pack is required for which it is necessary to preliminarily set a single level and save it after passing the required number of pulses, then the command on bus 29 is preceded by the appearance of a single potential on bus 30. This command sets trigger one in one state. At this, trigger 14 remains zero the state and the unit level from the output of the element AND 15 through the element OR 16 enters the bus 33 of the device. Following the command, bus 30 is followed by a command on bus 29, which sets three wires 14 to 1. It is forbidden to pass a single level through element 15. Next, the formation of a packet with a specified number of pulses, described above, is carried out . After the last pulse of the stack passes, trigger 14 is zeroed through the driver. At the first input of the element 15, a unit enters again, trigger 22 retains its unit state, and a unit level is again formed on the bus 33 of the device. A bundle with a single level at the beginning and zero at the end is formed as follows. According to the positive differential on the bus 31, triggers 20 and 22 are installed 48. At the same time, a unit level is formed on the bus 33. After forming a pack with a specified number of pulses, the pulse from the output of the imaging unit 8 zeroes through And 21 trigger 22, set the same4 on the device output to zero ypoiBeHb. The trigger 14 is turned around through the delay element 26, which is needed to eliminate the races (the trigger 22 must zero a little earlier than the trigger 14). Finally, a bundle with a zero level at the beginning and a single one at the end is formed as follows. Upon the arrival of a positive potential connecting via the bus 32, the trigger 24 is set to one. Further, on command 29, a packet of pulses is formed with a predetermined number of pulses, as described. At the end of the burst, a pulse from the output of the imaging unit 8 sets the trigger 22 through the element 25 to the unit and zeroes the trigger element 26 with a certain delay. The unit 26 forms a single level at the output of the device. The use of the invention allows to improve the diagnostic capabilities of the device for generating a pulse train without significant hardware costs and to use it not only for control, but also for adjusting the counting equipment, for example, tuning the counting impulse devices built on 7K triggers, scrapping backwards the front of the input signal, it is often necessary to fix the moment preceding the switching of that other high voltage. The proposed device allows to simulate the leading edge and the top of the desired pulse. Thereby, the state immediately preceding nos. the switching point of that bit of another bit, which is advantageously noted by the proposed device from a known

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Claims (2)

1. DEVICE FOR FORMING A PULSE PULSE, comprising a pulse generator, a single pulse generator, a packet trigger, a binary counter, a comparison unit, a first AND element, a first OR element, a first driver, an NAND element, a reset bus, and a group of driving buses, which connected to the first group of inputs of the comparison unit. the second group of inputs of which is connected to the outputs of the binary counter, the output of the single pulse generator is connected to the clock input. a pack start trigger, the direct output of which is connected to the first input of the first AND element, characterized in that, in order to expand the functionality, four triggers are introduced into it, the second and third elements are OR, the second, third, fourth and fifth · formers, the second third and the fourth element And, four control buses and a delay element, the output of which is connected to the first inverse input of the installation to zero of the first trigger, the second inverse input of the installation to which zero is connected to the reset bus, with inverse inputs of the installation to Only the second, third, fourth triggers and with the first input of the AND-NOT element, the second input of which is connected to the output of the first driver, with the input of the delay element and with the inverse inputs of the second and third AND elements, the direct inputs of which are connected respectively with the direct outputs of the second and fourth triggers ·, the outputs of the second and third elements AND are connected respectively to the direct inputs of the installation to zero and to the unit of the third trigger, the direct output of which is connected to the first input of the fourth element And, the output of which is connected with the first input of the second OR element, the second input of which is connected to the output of the first AND element and with the clock input of the binary counter, the direct input of the zero setting of which is connected to the output of the AND-NOT element, with the direct input of the zero setting of the trigger of the pack start, whose inverse output is connected to the information input of the trigger trigger pack, the second input of the first element And is connected to the output of the pulse generator and to the first input of the single pulse generator, the second input of which is connected to the first control bus. and with the input of the second driver, the output of which is connected, with the inverse input of the unit to the unit of the first trigger, the inverse output of which is connected to the second input of the fourth AND element, the second and third control buses are connected respectively to the first and second inputs of the third OR element, the output of which is through the third the shaper is connected to the inverse input of the unit to the unit of the third trigger, the inverse inputs of the unit to the unit of the second and fourth triggers are connected respectively to the outputs of the fourth and fifth formators lei, the inputs of which are connected respectively to the third and fourth control buses, the output of the comparison unit is connected to the input of the first driver. 2. The device according to claim 1, wherein each driver comprises an AND-NOT element and an odd number of HE elements connected in series, the input of the first and the output of the last of which are connected respectively to the first and second inputs of the AND-NOT element, the output of which connected to the output of the shaper, the input of which is connected to the first input of the element AND-NOT.