SU1228235A1 - Pulser - Google Patents

Abstract

The invention can be used in devices for controlling various digital devices. The purpose of the invention is to increase the reliability of the pulse generator. The pulse generator contains a crystal oscillator 1, a pulse counter 2, delay element 3, setup block 4, AND elements 5.6, program blocks 7, 8, program setting blocks 9.10, trigger 11, elements OR 12.13, AND element 14, output 15. The increase in reliability is achieved due to the fact that the delay element 3 synchronizes the operation of the comparison blocks 7, 8, which eliminated spurious signals from the outputs of the trigger 11, the AND element 14 and the initial installation block 4, the work of which is synchronized by pulses from the output of element 3 This eliminated the possibility of forming a shortened pulse at the generator output. The description shows an example of the execution of block 4 of the initial installation. 2 Il. (L

Description

The invention relates to a pulse technique and can be used in devices for testing and controlling various digital devices.

The purpose of the invention is to increase the reliability of the pulse generator.

Figure 1 shows the structural diagram of the pulse generator; Fig. 2 illustrates an example of the construction of a setup block.

The pulse generator contains (figure 1) crystal oscillator 1, the output of which is connected to the counting input of the counter 2 pulses and through the delay element 3 to the input of the unit 4 of the initial installation and to the second inputs of the elements 5 and 6. The outputs of the counter 2 are connected to the second groups of inputs blocks 7 and 8 of the comparison, the first groups of inputs of which are respectively connected to the outputs of the first and second blocks 9 and 10 of the program task.

The outputs of blocks 7 and 8 of the comparison, respectively, are connected to the third inputs of the AND 5 and 6 elements, the first inputs of which are respectively connected to the direct and inverse outputs of the trigger 11. The output of the AND 5 element is connected to the input R of the trigger 11 and the first input of the OR 12 element, and the output element AND 6 - to the first input of the element OR 13 and the second input of the element OR 12, the third input of which is connected to the second input of the element OR 13 and the inverse output of block 4 of the initial installation, and the output of the element OR 13 - to the input S of the trigger 1I, the output of the element OR 12 is connected to the input reset and counter 2, and the direct output of the initial installation unit 4 is connected to the first input of the element 14, the second input of which is connected to the direct output of the trigger 11, and the output is the output 15 of the generator.

Unit 4 of the initial setup contains (Fig. 2) a voltage divider 16 of pi.tani consisting of a resistor 17 and 18, a capacitor 19 and a Schmitt trigger 20 connected in series, an inverter 21 and a trigger 22.

The pulse generator works as follows.

When the power is turned on, the trigger 22 is set to the zero state. The low potential from the direct output of block 4 of the initial installation closes the element I 14 at the first input,

thus, for the duration of the generator in the initial state, the formation of pulses at its output 15 is prohibited,

The high potential from the inverse output of block 4, broadcast through the elements OR 12 and 13, sets counter 2 to the zero state, and trigger II to the unit state. Element And 5

It turns out to be open at the second input by a high potential from the direct output of the trigger 11, and element 6 is closed at the second input by a low potential from the inverse output of the trigger 11.

When the capacitor 19 is charged to a value sufficient to trigger the Schmitt trigger 20, a zero signal is output from the input R of the trigger 22

A low potential is applied to the input K, and a high potential to the input I through the inverter 1.

The nearest pulse coming from the output of the crystal oscillator 1 through

the leading edge delay element 3 sets the trigger 22 switched on according to the latch trigger circuit in a single state. Low potential with inverse output of block 4 allows

the operation of counter 2 and puts the trigger 11 in the information storage mode. The high potential from the direct output of block 4 opens element I 14, a high potential appears at its output — the formation of the first pulse begins at the output 15 of the generator. Thus, the formation of the leading edge of the first pulse at the output 15 of the generator occurs on the leading edge of the first after the removal of the signal

the initial setup of the pulse from the output of the element 3 delay.

Delay time with the pulse of the crystal oscillator 1 by the element 3 delay is selected from the condition

 St-g / iox-cc / iax

R

where t is the maximum time neV 1 i mtl KS

triggers trigger 2;

 Semds is the maximum propagation delay of the signals by blocks 7 and 8 compared to; T is the period of the following pulses of the quartz generator I.

When condition 1 is fulfilled, spurious pulses that may occur at the outputs of blocks 7 and 8 of comparison due to different switching times of the triggers of counter 2 will not pass to the outputs of elements 5 and 6.

The pulses from the output of the crystal oscillator 1, arriving at the counting input of counter 2, change its state. When the counter code 2 reaches equality with the number code set in block 9, a high potential appears at the output of block 7. The closest impulse from the output of the delay element 3 arrives at the output of the element 5, threw the counter 2 and the trigger 11. At this, the high potential from the inverse output of the trigger 11 opens at the second input of the element 6, and the low potential from the direct output of the trigger 11 closes at the second input elements And 5 and 1A. At the output 15 of the generator, the leading edge of the first pulse is formed, and pause formation begins. Thus, when the generator is turned on, the leading and trailing edges of the first pulse are formed synchronously with the leading edges of the pulses from the output of the delay element. no shortening of the first pulse occurs.

Upon reaching, when refilling the counter 2 code, an equality with the number code set in block 10, a high potential appears at the output of block 8. The closest impulse from the output of the delay element 3 arrives at the output of the AND 6 element, swings the counter 2 and sets the trigger 11 into one state. At the generator output 15, a pause is completed and the leading edge of the second pulse is formed. Next, the generator operation process is repeated.

The delay element 3 synchronizes the operation of blocks 7 and 8 on the output, which eliminates spurious signals from the trigger 11 inputs from their outputs element AND 14 and the initial installation block 4, which is synchronized with pulses from the output of the delay element 3, eliminates the possibility of generation at the generator output shortened pulse.

Claims (1)

Invention Formula The pulse generator containing the crystal oscillator, the first and second And elements, the first inputs of which are respectively connected to the direct and inverse outputs of the trigger, the first and second blocks of the program setting and the pulse counter are distinguished) so that, in order to increase the reliability in operation, the third element I was inserted into it, the first and second OR elements, the delay element, the initial setup block, and the first and the second comparison blocks, the first groups of inputs of which are respectively connected to the outputs of the first and second blocks of the program setting, and the second groups of inputs are connected to the outputs of the pulse counter, the counting input of which is connected to the output of the quartz oscillator and through the delay element to the input of the initial setting block and to the second the inputs of the first and second elements are And, the third inputs of which are respectively connected to the outputs of the first and second blocks of the comparison, the output of the first element And is connected to the input of the R-flip-flop and the first input of the first OR, and the output of the second element And is connected to the second input of the first element Sh1I and the first input of the second element OR, the output of which is connected to the input of the S-flip-flop, and the second input of the second the OR element is connected to the third input of the first OR element and the inverse output of the setup block, the direct output of which is connected to the first input of the third element And, the second input of which is connected to the forward output of the trigger, and the output of the third element AND is the generator output, the output of the first element OR is connected to the zero input of the pulse counter. Editor M.Tovtin Compiled by R. Matveeva Tehred G. Gerber Order 2295/56 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Polygraphic enterprise, Uzhgorod, st. Project, 4 2 Proofreader S. Shekmar