SU383209A1 - Phase impulse device - Google Patents

Description

one

The invention relates to pulse technology and can be used in telemechanics and computational techniques.

The known device, which is a T1 three-phase digital sensor, containing a three-fold triggers register, a decoder, logic “NOT,” OR, “AND and Indicator ycTipo CTBO, P; p, and unchanged from a certain sequence input signals, i.e., at the moment when the signal arrives, after which it disappears and the next signal appears, the potential signal for the whole time of the input signals of the specified sequence.

The purpose of the invention is to increase the reliability of phase control between any two signals that follow each other through different inputs.

In contrast to the known device, in the proposed device, an output pulse signal is generated at each instant of changing input signals of the specified sequence, which is important for reliable phase control.

In the proposed device, which contains additional static, coincidence circuits and inverters, and a three-stroke generator of shifted impulses, the first INPUTS of the even three-input coincidence circuits.

the control registers are jointly connected to the output of an additional static trigger, one of the inputs of which through an inverter is connected to the first inputs of the odd two-input coincidence circuit controlling the register, and to the clock output of the three-stroke shifted pulse generator, the other output of which is connected to the second input of the above trigger through another scheme

matches associated with register output; the second inputs of the even match circuits controlling the register are jointly connected to the third clock output of the said generator, the rest of the even and odd moves

matching circuits in pairs. connected to the inputs of the device, and between the outputs of the specified matching circuits and zero inputs of the register triggers include / sequentially connected additional matching circuits

and inverters.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 shows the timing diagram of the device.

The device contains a register on static triggers I, 2, and 3 with separate inputs, an additional static trigger 4 with separate inputs, a "AND-NOT 5-JQ" matching circuit, which is controlled at the inputs

register, the first inputs of even circuits 6, 8 and 10 coincidence which are jointly connected to the output of trigger 4, one of the inputs of which through inverter 11 is connected to, ne, p1 inputs of odd coincidence circuits "AND-NOT 5, 7 and 9 and clock output 12 of a three-stroke shifted pulse generator 13, another output 14 of which is connected to the matching circuit "AND-NO 15, controlling trigger 4, another of the inputs of the matching circuit," AND-NOT 15 connected to the output 16 of the register, the second inputs of the matching circuit, "AND NOT 6, 8 v (10 are jointly connected to the third clock output 17 of the generator 13, the remaining inputs of even 6, 8, and 10 and odd 5, 7, and P coincidence circuits are pairwise connected to the inputs 18, 19, and 20 of the device, and additional outputs are included between the outputs of the specified 5–10 coincidence circuits and zero inputs of the flip-flops / -3. matches "AND-NOT 21, 22, 23 and inverters 24, 25, 26. The device also contains matching schemes" AND-NOT 27-30, located at the output of the register I-5, output 5 / and reset bus 52. The device is running in the following way. The initial state of the circuit is set by the IM | Pulse of low potential, coming through the reset bus 32. In this case, the inputs 18, 19 and 20 are the LOW potential of the input pulses (see Fig. 2, a, b), and from the outputs 12, 14, and 17 of the generator 13, clock pulses are received, shifted relative to each other (see Fig. 2 , g, d, e). At the output of the register, trigger 4 and the output 31 of the device, a low potential is established, and the output of the circuit // matches will produce pulses that are inverted with respect to the pulses coming from the clock output 12 of the generator 13. In the case of, for example, a high potential is detected at the input 18, coinciding with the first clock pulse at the output 12 of the generator 13, through the coincidence circuit 5, the trigger 1 of the register is activated and the initial state of the trigger 2 is confirmed through the circuit 22, the match and the inverter 25 (see Fig. 2, g, g). At the next moments of the occurrence of the first clock pulse when there is a high potential at the input 18 of the device, the circuits 5 and 22 of the match and the inverter 25 will work in the same way, controlling the 1 2 register triggers and resetting in the absence of the first clock pulse from the generator output 12 13. At the time of the occurrence of, for example, the next high potential at the inlet 19 of the device (see Fig. 2, b) —without the absence of a signal at input 18 — by matching with the first clock pulse at the output 12 of the generator 13 through the circuit 7 audio triggered flip-flop 2 register "confirmed initial state after three ggera 3 coincidence circuit 23 and an inverter 26 (see. FIG. 2, s, s). At the same time, a high potential appears at the output 16 of the register, which prepares a matching circuit 15 for operation. In the absence of a high potential of the clock pulse at the output 12 of the generator 13 of the circuit 7 and 23, the coincidence and inverter 26 are in the initial state. At the moment the next second clock pulse arrives at the output 14 of the generator 13, a trigger 4 is triggered (see Fig. 2, k) through the coincidence circuit 15, and a pulse is formed at the output 31 of the device (see Fig. 2, l), inverted relative to second clock pulse. In this case, a coincidence circuit 6 is prepared for operation. Thus, at the output 31 of the device, a pulse was formed in duration, commensurate with the second clock pulse of the generator 13 and characterizing the phase of the second signal following the first signal at the inputs 19 and 18 of the device, respectively. At the time of receipt of the next third clock pulse at the output 17 of the generator 13, the trigger / register is reset to the initial state via circuits 6 and 21 and the inverter 24. At the output 16 of the register, a low potential is set (see Fig. 2, g). In the absence of the third clock pulse at the output 17 of the generator 13 of the circuit 6 n 21, the matches and the inverter 24 are reset. At the time of receipt of the next first clock pulse at the output 12 of the generator 13, the trigger 4 (see FIG. 2, k) is reset, via the inverter 11. When, for example, the next signal arrives at the device input 20, it coincides with the first clock pulse pa The output 12 of the generator 13 in the same way triggers the trigger 3 (see Fig. 2 and) of the register through the coincidence circuit 9 and confirms the initial state of the trigger 1 through the coincidence circuit 21 and the inverter 24. Since the trigger 2 is turned on, the high potential from the output 16 is register prepared for the coincidence circuit 15, the output of which follows the second clock pulse at the output 14 of the generator 13 sformiruets output pulse. This triggers trigger 4 and prepares the circuits 5, 8 and 10 for operation on the third clock pulse at the output 17 of the generator 13 for resetting the previous trigger 2 register to the initial state, and for the nearest first clock pulse the trigger 4 is set, and etc. In the case when the specified sequence of signals arriving at inputs 18, 19 and 20 of the device changes, for example, after the signal at input 20 a signal appears at input 19, then at input 18 of the device, etc., the circuit works as follows th. After setting the trigger 2 register (see Fig. 2, g) and the trigger 4 to the initial state with the subsequent absence of a signal at input 20 (see Fig. 2, b) and the appearance of the signal at output 19 (see Fig. 2 , b) coincidentally with the first such impulse at output 12

the generator 13 triggers trigger 2 and the trigger 3 of the register is reset. Upon receipt of the following clock pulses from the generator 13 to the entire time the signal is present at the input 19, the circuit does not change its state, and the output 31 of the device does not generate an output signal, which indicates a phase change between two successive signals. Upon further succession of the signals at the inputs 18, 20 and 19 lt.d., in this sequence, only one of the flip-flops 1, 2 and 3 registers works, and the signals at the output 31 of the device are not generated.

Thus, the proposed device provides reliable control of the phase between any two signals that follow each other along different inputs, thereby generating pulse signals at the output at each instant of changing input signals, unlike the known device, in which a potential signal is generated that only qualitatively characterizes the presence of input signals during the entire time of their arrival.

The proposed device makes it possible to simplify the programming of digital computing machines that control the phase of the input signals, and to reduce the amount of their RAM.

The subject of the invention is a Phase pulse device, made on potential elements, containing a three-bit register on static triggers, inverters and even and odd coincidence circuits, characterized in that, in order to increase the phase control between any two successive signals along different inputs, it contains

additional static trigger, coincidence circuits and inverters, and a three-stroke shifted pulse generator, the first inputs of even-numbered coincidence circuits are connected to the output of an additional static trigger, one of the inputs of which is connected to the first inputs of odd-numbered coincidence circuits and a clock pulse shifter whose other output is connected to

the second input of an additional static trigger through a matching circuit, associated with the output of a three-bit register; the second inputs of the even coincidence circuits are connected together. They are connected to the third clock output of the three-stroke shifted pulse generator, the remaining inputs of the even and odd coincidence circuits are pairwise connected to the inputs of the device, and between the outputs of these coincidence circuits and the zero inputs of static triggers

a three-bit register, connected in series, additional matching circuits and inverters.

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