SU571915A1 - Pulse frequency divider with adiustable division factor - Google Patents

Description

(54; PULSE FREQUENCY DIVIDER WITH ADJUSTABLE DIVISION COEFFICIENT

This invention relates to a pulsed technology.

A known frequency divider with an adjustable division factor, containing a reversible counter with n + 1 counting cells, connected to each other through gate cells. Both outputs of each cell except the last one are connected to a switching device, the parallel inputs of which are connected to the main or additional-Q inputs of each cell. The structure of the output block is introduced logical elements NOT AND AND NOT OR l.

This divider is complicated.

Closest to the proposed delj jj gel, which contains two pulse frequency multipliers, each of which consists of series-connected triggers and potential-pulse keys, one input of each of which is connected to the output jO of the corresponding multiplier trigger, the second inputs are connected to the signal sources of the setup the divider and the divisible division factor, and the outputs are combined, with the outputs of the keys of the first frequency multiplier 25

the pulses are connected to the first input of the Inhibit logic element, the second input of which is connected to the input source 2J.

The disadvantage of this divider is the inadequate control of signals in binary-decimal code.

Claims (2)

The purpose of the invention is to control the signal divider in a binary-tenth code - this is achieved by the fact that a frequency divider containing two pulse frequency multipliers each consists of series-connected triggers and potential-impulse switches, one input of each of which is connected to the output of the corresponding trigger multiplier , the second inputs are connected to the terminals of the signal sources of the installation of the divisor and the dividend division factor, and the outputs are combined, with the outputs of the keys of the first pulse frequency multiplier with Connected to the first input of the Ban element, the second input of which is connected to the input source, two impulse adders, four additional potential key switches, are introduced, and the impulse adders between the output of the logic element Prohibit the inputs of smart switches: d-: t:; chyulsov, the first entrances of the two; The solar keys are connected to the outputs of the second and third triggers of the first smart switch, and the outputs are connected to each other by themselves and connected to the control output & The first one of the first pulse adder, the third and fourth secondary switches, are connected to the second third triggers of the first frequency multiplier, and their terminals are connected to each other and connected to the control input of the second one (Pulse totalizer, the second inputs of all additional keys are connected to the source control signal. A structural divider circuit is shown in the drawing. The divider contains Binary multiplier i, consisting of 2 ™ 5 flip-flops and potentially impulse keys 6-9, to the inputs Significant sub-signals are the numbers of the dividing coefficient, binary multiplier 14, consisting of triggers 15-18 and impulse potential keys 19-22, whose inputs 23-26 receive a signal of the division factor indicator; logical element Ban 27, additional potentials 1 -pulse switches 28-31, impulse cyMMaTOffci 32, 33. Input 34 sends an input signal, input 35 sends a control signal, output signal supplies output 36. The power sources and signals are not shown in the diagram. The principle of operation of the divider is as follows When applying to the inputs 1O-13 and 23-26 binary codes of the numerator P and the denominator and the coefficients of the distribution on input 35, it is necessary to set a zero signal; then the keys 26-31 are locked and the device implements the division ratio J i P / Q-S -f, the numbers Р and Q KOTOporo are given by double codes. If the numbers P and Q are given by binary-decimal codes, a decimal signal is sent to go 35 allowing the impulses from the key outputs to the impulse adders 32 and 33. Consider the operation of the binary multiplier (for example, 2; signal. When the adder receives 33 ten pulses, the trigger 15 receives 16 pulses.On one overrun of the counter formed by triggers 15-18, the number of pulses received by the knot of the AND set at the inputs 23-26 comes to the output of the keys. gfie q 10 mouth Code 0101 is repaired, and 1O pulses are passed to the output. The device has wider functionality and allows you to set the division factors specified by both binary and binary "-Dan codes. The formula for the frequency of pulses with an adjustable division factor, containing two pulse frequency multipliers, each of which consists of series-connected triggers and potential impulse keys, one input of each of which is connected to the output of the corresponding trigger mind ozhitel, second inputs connected to the terminals SET signal sources; ki divider and dividing a dividend ratio. and the outputs are combined, and outputs; the keys of the first multiplier of the pulse impulse are connected to the first input of the Ban element, the second input of which is connected to the input signal source, which is mainly due to the fact that, in order to control the divider by signals in the binary-decimal code, two impulse summers are entered into it and four additional potential-pulse keys, with pulse adders connected between the output of the Inhibit logic element and the inputs of the frequency-pulse multipliers, the first inputs of two additional keys are connected to the outputs of the second the first and third triggers of the first frequency multiplier, and their outputs are interconnected and connected to the control output of the first pulse adder, the first inputs of the third and fourth additional switches are connected to the outputs of the second and third trigger of the second frequency multiplier, and their outputs are interconnected and connected to the control input of the second pulse adder, wherein the second inputs of the additional keys are connected to the terminal of the control signal source. The sources of information taken into account in the examination: 1. German patent number 1269656, 21 azb / 22, from 19L2.68. 2. The copyright certificate number 316198, and 03 K 23/02. 04/17/68.