SU809156A1 - Device for sequential unities extraction from n-bit code - Google Patents

Description

(54) DEVICE FOR THE SEQUENTIAL ISOLATION OF UNITS FROM P-DISPLAY CODE

one

The invention relates to computing and can be used in priority circuits, in hardware control systems of computer facilities, in associative memory devices.

A device is known for sequentially allocating units from a given n-bit binary code, which contains two serially connected registers of a unit allocation unit, a unit selection exclusion unit, a converter of the number of the allocated unit into the binary code, and the binary code of the bit number of the selected unit 1.

The drawbacks of the device are its complexity due to the use of an encoder, a decoder, as well as a large number of information links, which increase sharply with increasing source code size. The complexity of the device determines its lowered hope.

A device for a sequence of extracting units from a given p-bit binary code is known, which contains the main, auxiliary and additional registers executed on the flip-flops, the unit for allocating units made in. of the same type of cell, each of which consists of an OR element and two AND 2 elements.

The disadvantages of this device are the complicated mode of its use, due to the fact that to allocate each unit requires a repeated cycle of accessing the storage device storing the source code, and re-submitting the source code to select the second, third, etc. leads to a decrease in device performance), the inability to determine (without additional external circuits) whether the selected unit is the last, the narrow functional purpose of the device and the impossibility of its use olzovani other computing tasks except vy5 dividing units of n-bit code.

The purpose of the invention is to expand the functionality of the device by performing the functions of the generator of the traveling unit, the shifter and the memory.

The goal is achieved by the fact that in the device for sequential selection of units from a n-bit code containing n bits, each bit of the device contains the main and auxiliary triggers, the first and second elements AND, the element OR, the fourth, fifth, the sixth, seventh and eighth elements And, with each discharge the first input of the first element And connected to the first input bus device, the first input of the second element And connected to the second input bus device, the outputs of the first and second elements And connected respectively, the first and second inputs of the main trigger, the inverse output of the main trigger connected to the first input of the third element And, and the direct output to the first input of the fourth element And, the second input of the fourth element And connected to the third input, device bus, the outputs of the third and fourth elements AND are connected respectively to the first and second inputs of the OR element, the output of which is connected to the first inputs of the fifth and sixth elements AND, the second inputs of which are connected respectively to the fourth and fifth input buses y The devices, the output of the fifth and sixth elements And are connected respectively to the first and second inputs of the auxiliary trigger, the direct output of which is connected to the first inputs of the seventh and eighth elements And, the second inputs of which are connected respectively to the sixth and seventh input buses of the device, the output of the seventh element And connected to the second inputs of the first and second elements And, the output of the eighth element And connected to the corresponding discharge output of the device, the second input of the third element And the first discharge of the device n to the first input of the device, and the second input of the third element AND the subsequent bit is connected to the output of the third element AND the previous bit, the third input of the OR element of the first bit of the device is connected to the second input of the device, and the third input of the OR element of the subsequent bit is connected to the output the seventh element And the previous bit, the output of the seventh element And the last bit of the device is connected to the first output of the device, the second output of which is connected to the output of the third element And the last bit of the device, first first and second inputs of each flip-flop main discharge are respectively connected to first and second inputs of the mounting device, and the first and second inputs of the auxiliary flip-flop of each bit are respectively connected to third and fourth inputs of the mounting device.

The drawing shows a functional diagram of an apparatus for sequentially separating units from an n-bit code. The device contains the first, second, third, fourth, fifth, sixth, seventh and eighth elements AND 1-8, triggers 9 of the main register, triggers 10 of the auxiliary register, first, second, third, fourth, fifth, sixth and seventh input

device buses 11-17, first and second inputs 18 and 19 of the device, first and second outputs 20 and 21 of the device, first, second, third and fourth installation inputs 2225 of the device, and discharge bits 26 of the device.

The device works as follows.

1. Isolation function.

The first clock on information buses 11 and 12 to the main register is a z-pin binary. When using a paraphase information input, the zero state of the main register is not preset and there is no need for input 23. Simultaneously with the first clock of the code recording, the auxiliary register is set to a single state along the bus 24.

The second clock is sent to the busbar 15 and the input 18, which is passed through a signal that passes sequentially through the chain of all third elements AND to the first unit in the main register, and the output signal of the third elements AND through the OR elements and fifth elements AND sets the corresponding triggers of the auxiliary register to zero the

Example. Let the entire device have a dimension of one byte (eight bits) and the code 00010110 is applied (it will read 0 from left to right). Simultaneously with the installation of this code in the main register, the auxiliary register will have the code 11111111. After the signals are fed to the inputs 15 and 18 of the auxiliary register will be 00011111. The third clock cycle with the signal applied to buses 12 and 16 on the auxiliary register is fixed The key is stored on the main register, i.e., the code 00000110 remains, prepared to allocate a subsequent 0 unit.

2. The generator function of the running unit.

At given code bits, the signal "1 at the first input, then at the second, and so on until n, then the sequence is repeated, starting from the first input, etc." is generated.

This function is implemented by the proposed device, if an external circuit connects output 20 to input 22. 50 Before starting operation in this mode, a single state setting signal in the main register is given or the code from one unit is written to the main register via parallel information inputs.

Claims (1)

5 Then the unit selection mode is performed. On every third clock cycle, at output 20, the next unit will appear. After the last unit is selected at output 20, the state of all units in the main register will be automatically restored and the operation will be repeated. 3. The function of the shift register to the right (or left). On the first clock cycle, the source code is received in the main register, and at the same time the auxiliary register is set to the zero state by a signal at input 25. The second clock with signals to the buses 13 and 14 is the transfer of the code from the main to the auxiliary register. The third clock tick on the buses 14 and 16 is the shift of the code in the auxiliary register. On the fourth clock cycle with the signal applied to the buses 11 and 16, the code is shifted to the right by one bit of the code in the main register. To eliminate possible races during the shift operation, tires 14 and 16 are given a signal with a duration of no more than four delays in AND, OR. A shift to the left on the device is possible if the connection from the seventh elements AND to the input of the OR circuit is made from right to left. 4. Memory functions of the firmware automaton. In firmware automata with a different implementation principle of combinational circuits, for example, on programmable logic arrays, AND, OR elements, tunable media, etc., it is required to eliminate memory races with a simple transfer function of the n-bit code from one register to another with the separation in time of the operations of receiving the code in the first register and transmitting the code to the second register according to a special tact. This function is implemented by the device as follows. After receiving the code in the main register, the code is transmitted to the auxiliary register when a signal is applied simultaneously to buses 13 and 14. Signals are captured via parallel outputs 26 when the signal is fed to bus 17. 5. The function of the stack memory. The integration of m devices by a connection into a single bus | 3 and a second bus 15 is achieved. The bit outputs of the nth device are connected to the information inputs 11 of the device. We will get a stack memory of 2m of the nth bit numbers. After the n-bit code has been sent to the input of the first device, the shift in the whole stack of 2m registers takes two ticks. In the first cycle, an intermediate shift is carried out within each device when the signal is sent to bus 13 and 14. In the second cycle, the codes from device 1 are transferred to device 2 from device 2 to device 3 and g. when the signal is applied to the inputs 17. The removal of the code, like the usual stack, is performed from its top, i.e. from the t-th device. Note that the memory received from the stack has, compared to the existing types of stacks, the advantage of simultaneously allowing the above described functions to be performed over 2t-numbers with a bit size n, i.e. it is essentially a specialized parallel processor. The effectiveness of the invention consists in expanding the functionality of the device by performing the generator functions of the running unit, the functions of the shift register, the memory functions of the microprogram automat and the stack memory functions, as well as increasing the device speed in the task of sequential allocation of units from the p-bit code. as it does not require the re-submission of the original p-bit code to highlight the second, third, etc. units. Apparatus of the Invention A device for sequentially separating units from an n-bit code comprising n bits, with each bit of a device containing main and auxiliary triggers, first and second And elements, and OR element, characterized in that, in order to expand the functionality of the device by performing the functions of the generator of the treadmill, shifter and memory, the fourth, fifth, sixth, seventh and eighth And elements are added to it, and in each section the first input of the first element And It is connected to the first input bus of the device, the first input of the second element I is connected to the second input bus of the device, the outputs of the first and second elements I are connected respectively to the first and second inputs of the main trigger, the inverse output of the main trigger I is connected to the first input of the third element I, direct output - with the first input of the fourth element And, the second input of the fourth element And connected to the third input bar of the device, the outputs of the third and fourth elements And connected to the first and second inputs, respectively and OR, the output of which is connected to the first inputs of the FIFTH and sixth elements AND, the second inputs of which are connected respectively to the fourth and fifth input buses of the device, the output of the fifth and secondary elements AND are connected respectively to the first and second inlets of the auxiliary trigger, direct the output of which is connected to the first inputs of the seventh and eighth elements And, the second inputs of which are connected respectively to the sixth and seventh input buses of the device, the output of the seventh element I is connected to the second inputs of the first and second elements I, the output of the eighth element I is connected to the corresponding discharge output of the device, the second input of the third element I of the first bit of the device is connected to the first input of the device, and the second input of the third element And the next, its discharge is connected to the output of the third element AND the previous one of its discharge, the third input of the element OR the first discharge of the device is connected to the second input of the device, and the third input coagulant or subsequent discharge connected to the output of the seventh AND gate of the previous discharge, the output of AND .sedmogo last discharge device is connected to the first output device. The second output of which is connected to the output of the third element AND of the last bit of the device, the first and second inputs of the main trigger of each bit are connected respectively to the first and second installation inputs of the device, and the first and second inputs of the auxiliary trigger of each bit are connected respectively to the third and fourth setting device inputs. Sources of information taken into account in the examination 1 USSR author's certificate No. 278215, cl. G 06 F 5/02, 1970. 2 USSR author's certificate according to application No. 2504715 / 18-24, class C. 06 F 5/02, 1977 (prototype).