SU645159A1 - Priority device - Google Patents

Description

(54) PRIORITY DEVICE

The aim of the invention is to reduce equipment.

The goal is achieved by the fact that the device contains To. Logical blocks, the i-bit register of the request is divided into / C groups, the elements OR are entered into each logical block, the second group of AND elements and the priority application analysis node, and the information inputs of each node analysis of the priority application is connected to the outputs of the bits of the same name group of the discharge register of the application, the control input of each node of the priority application is connected to the third OUTPUT of the control unit, in each logical block of the output of the analysis node the priority The second applications are connected to the corresponding inputs of the OR element and to the first inputs of the elements AND of the second group of elements AND, the second inputs of which are connected to the counter overflow output, the outputs of the elements AND of the second group of elements AND are connected to the single inputs of the corresponding bits of the l-bit output register and with zero inputs of bits of the same name of the L-bit register register, the output of the element OR is connected to the third input of the element I.

The structural scheme of the proposed device is shown in the drawing.

The priority device contains a block / control, a generator of 2 pulses, an output element OR 3, an n-bit register 4 for wok, an l-bit output register 5, logical blocks 6, each of which contains a priority register 7, an analysis node 8 for vki, the first group of 9 elements AND, element OR 10, element I / Y, counter -12, the second group 13 elements AND, the outputs 14 elements AND the second group, the first input / 5 devices, the second input 16 devices, the first group of inputs 17 devices , the second group of inputs 18 devices, the first output 19 devices, gr oup output device 20 outputs 2,1 '-bit register for wok.

Single inputs of n-bit register 4 request are connected to the first group of device inputs -17 (order signals). The output of the output element OR 3 is connected to the first output of the device 19, (the end of the work cycle) and to the first input of the unit / control, the second input of which is connected to the first input of the device J5 (start signal). The zero input of the L-bit register 5 and the third input of the unit / control are connected to the second input 1: 6 of the device (subscriber response signal). The output of the l-bit register 5 is connected to a group of outputs 20 of the device (output signals). The fourth input of the control unit is connected to the outputs of the l-bit register of the check. In each logical block 6, the inputs of the priority register 7 are connected to the second group of device inputs / i5 (priority codes).

The device works as follows.

Signals from the subscriber, whose priorities are determined by the priority codes of the groups listed in the priority registers and the priorities in the group, are fed into the corresponding bits of the l-bit register 4 applications. The start signal at input 15 is fed to the second input of control unit 1. The control unit 1 generates a signal at the first output, which opens elements AND groups of elements AND 9, providing a copying of priority codes from priority registers 7 to counters J2, and also generates a signal at the third output, which goes to the control inputs of the priority request analysis unit 8 which generates a signal corresponding to the highest priority subscriber in the group. This sigal through the element OR 10 and enters the third input of the element AND 7 / and the first inputs of the elements AND of the second group 13.

After sufficient time to write priority codes from the priority registers to the counters and for the analysis of priority applications in groups by the nodes 8, the block / control stops generating a signal at the first output, thereby closing the elements AND of the first group, and also generates a signal at the second output which arrives at the input of elements AND 11. Elements AND // are opened and the pulses from the generator 2 of pulses arrive at the counting inputs of those counters 12 that correspond to the groups from whose subscribers the input signals came in l-bit th register 4 for wok. The counting of pulses in the counters continues until the signal appears. overflow on the output of the counter in which the highest priority code was written. This counter uniquely identifies the highest priority group of subscribers.

When an overflow signal arrives at the input of the output OR 3 element, its output generates a signal of the end of the work cycle, which arrives as a service request signal to the device that subscribers are calling and to the first input block 1 of the control. The unit / control stops outputting signals at the second and third outputs, as a result of which elements 11 E close, pulses from the generator to the counters are stopped.

The counter overflow signal is also supplied to the second inputs of elements AND of the second group 13, as a result of which a signal is generated at the output of that element AND of the second group, the first input of which contains a signal from the output of the priority analysis analysis node 8. This signal from the output of the element And the second group J3 is fed to the single input of the corresponding bit of the output l-bit register 5, as a result of which one of the outputs of the group 20 of the outputs produces a signal corresponding to the subscriber selected for service in this cycle of operation. At the same time, the signal from the output of the element And the second group enters the zero input of the corresponding bit of the n-bit register 4 order, which is removed from the queue of the selected application.

When a response signal from the subscriber arrives at the input 16, the z / bit output register 5, counters 12 are set to zero, and the unit / control, if there are signals at the outputs of the 21 rt-bit register 4, produces control signals providing the beginning of a new cycle of the device.

Thus, the grouping of subscribers and the assignment of a logical block for the group to the calsd, and the use of the OR element, the priority application analysis node and the second group of AND elements in the logical block distinguishes the proposed priority device from the specified prototype, since it allows It does not reduce the total amount of equipment in the device.

Claims (2)

1. USSR author's certificate No. 458828, cl. G 06 F 9/18, 03/22/73. 2. USSR author's certificate, №475622, cl. G 06 F 9/18, 07/02/73. ha