SU1410098A1 - Device for controlling solid-state storage - Google Patents

Abstract

The invention relates to semiconductor memory devices (RAM) and can be used to create dynamic RAM control devices. The purpose of the invention is to simplify the device. The goal is achieved due to the possibility of automatic adjustment of the control unit Ш1 with cells on MOS transistors with different time ratios between the control signals, different number of control inputs, different operating modes, the introduction of fixed memory into the device 13 , register 14, element And 15. The device contains blocks 1, 2 of the input address and data, respectively, driver 3, generators 4 and 5, elements AND 6.7, elements OR 8.9, counter 10 regeneration addresses , trigger 11, encoder 12, block 13, register 14. 6 Il. (Lg

Description

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The invention relates to semiconductor memory devices (RAM) and can be used to create dynamic RAM control devices.

The purpose of the invention is to simplify the device.

FIG. 1 shows a functional diagram of the proposed device CTBaJ in FIG. 2-4 are examples of the implementation of a driver, a regeneration address and an address input block, respectively; in fig. 5 and 6 are a map of the distribution of the memory and address inputs and outputs of the memory block;

The device contains blocks for the input of address 1 and data 2, the driver 3, the first and second groups of generators 4 and 5 pulses, the first and second groups of elements 6 and 7, the first 8 and second 9 elements P1LI, the counter 10 of the regeneration addresses, the trigger 11 , the encoder 12, the block 13 of the permanent memory (ROM), the register 14 and the element And 15.

The shaper 3 contains the selector 16, the AND 17-20 elements and the D-flip-flops 21-24, with the inputs 25 of the selector 16 being the address inputs of the device, the input 26 being the enable input, and the inputs 27 being the information inputs of the device, the outputs 28 D- the flip-flops 21 are connected to the second inputs of the element OR 8, the outputs 29 of the D-flip-flops 22 to the fourth group of address inputs of the block 13 or ROM, the outputs 30 of the D-flip-flops 23 to the inputs of the counter 10 for the regeneration addresses, the outputs 31 of the jD-flip-flops 24 to the second the inputs of the Element Cent and 7. The imaging unit 3 carries out the initial installation of the device b for depending on the type used (semiconductor memory (PP).

Counter 10 addresses regeneration Kfig. 3) contains three binary four-bit counters 32, elements AND 33-36 and element OR 37, input 38 of the first counter is connected to the output of the regeneration trigger 11, inputs 39 of the counter 10 of the regeneration addresses are connected to the outputs 30 of the form-) actuator 3 , the outputs 40 are connected to the second group of inputs of the address input block 1.

The unit 1 input address {{FIG. 4) multiplexers 41 are included, having an organization of 3x1, where the inputs of the device are connected to the inputs 42.

 corresponding to the lower half of the address, inputs 43 of the device are connected to the inputs corresponding to the upper half of the address, outputs 40 of the regeneration address counter 10 are connected to inputs 44, inputs 45 are the outputs of the device and connected to the address inputs of the control panel. Inputs 46 are connected to the second group of outputs of register 14 and determine the sequence of connecting the lower half of the address, the upper half of the address, or the address of regeneration to the address inputs of G1.

FIG. 5 shows the memory allocation map of block 13, for example, a ROM with the organization of 2048 x x8 bits can be used. The address zones 47, 48, and 49 contain information that controls the W1 times: of the type, the address zones 50, 51, and 52 are the word sets that control the write mode, the address zones 53, 54, and 55 are the word sets that control the read mode, and address zones 56, 57, and 58 are word sets that control the regeneration mode.

- In FIG. 6 shows the distribution of the address inputs and outputs of block 13. The high bits 59 of the address word select the control word area of block 13, intended to control a certain type of AE, the number of address inputs 59 being determined from the formula

L + l.

where L is the number of address inlets,

Dov 59;

p is the number of types of controllable PP.

The address word bits 60 selects the control word area of the ROM 13 corresponding to a certain control mode of the control panel — Write, Read, Regeneration, and the number of address inputs 60 is determined by a similar formula.

The low bits 61 of the address word select the next control word from block 13, corresponding to a certain cycle of the control PP.

The outputs 62 of the unit 13 are connected to the second group of inputs of the register 14, which is a register with a parallel entry of information on the gate.

The device operates as follows.

Before you start working with PC, the control device is configured for a specific type of accumulator, for which the shaper 3 by signals Record to the enable input in accordance with the addresses to the group of address inputs that select trigger groups 21-24 are recorded through the group of information inputs The information that determines, respectively, the operating frequency of the AH, the type of AH, the maximum address of the regeneration, and the frequency of the regeneration. The read resolution signal, which arrives at the first input of the encoder 12, selects in the ROM 13 a memory area corresponding to the Read mode of the software type selected by the driver 3, and from the output of the ROM 13 to the register 14, the first control word is written to the clock signal the first input of register 14 from the OR element 8. The control word contains control signals of the control unit, control signals of the address input unit 1 and data input unit 2, and regeneration mode control signals, and the control signals of the control unit, input block 1 and block 2 are TERM signals applied to the third, fourth and fifth inputs of the ROM Tide

13 and choosing from the ROM 13 the next control word, which is written into register 14 by the next clock signal received from the element OR 8. From the fifth output of the register

14, the second input of the element 15 is outputting a signal prohibiting the regeneration request signal from the output of the trigger 11. The regeneration trigger 11 is set on the first input by a signal passing through the elements 7 and OR 9 from the generator 5.

The last control word of the Read mode allows the Regeneration signal from the output of the regeneration trigger 11 to pass through the AND 15 element to the priority input of the encoder 12; as a result, regardless of the control signals Write or Read on the first or second inputs of the encoder 12, the device issues control signals to the PP, corresponding to the regeneration mode, since in the ROM 13, the control word area is selected

regeneration mode, From the output of the trigger 11 to the second input of the counter 10 receives the signal to increase the address

regeneration, per unit. The regeneration address from the outputs of the counter 10 is fed to the second group of inputs of the counter 10, which, according to the control signals supplied to the third group of inputs

from the second outputs of register 14, transmits this address to the address inputs: PP. The last control word of the regeneration mode contains the reset signal of the trigger 11, arriving at its

BTOpo i input from the fourth output of the register 14.

When referring to another type of PP, the device is configured by setting the driver 3, i.e.

at the same time, control information is written to the trigger groups 21-24, which determines the required operating frequency of the accumulator corresponding to this type of AE, the required maximum regeneration address and the required regeneration frequency.

Claims (1)

Invention Formula A semiconductor memory control unit containing a driver, address and data input blocks, first and second groups of pulse generators, first and second elements OR, the first and the second group of elements are AND, the regeneration address counter, the trigger, the group of address, the driver inputs are combined with the first group of address inputs of the block. input address and is a group of address inputs of the device, a group of information inputs of the driver, respectively, combined with the first group of information inputs of the input block data, is a group of information inputs of the device, the enable input of the imager is the input of the resolution of the recording device, the first group of outputs of the imager is connected respectively to the first inputs of the Elements AND of the first group, the second inputs of which are connected to the corresponding outputs of the first group pulse generators, and the outputs are connected to the inputs of the first element 1ShI, the second group of address inputs of the address input block is connected to the outputs of the regeneration address counter, the installation input of which is connected to the first | output of the imaging device, and the counting input - with the trigger output; the input of the ko-iTcporo installation is connected to the output of the second element OR, whose inputs are connected to the outputs of the second group of elements AND, the first inputs of which are connected to the outputs of the second group of pulse generators, and the second inputs - respectively with the second group of exits formirovat-jq The output groups of the address and data input blocks are respectively the address and information output device groups of the device, characterized in that, for the purpose of simplification. device, an encoder, a block of permanent memory, a register and an element, whose first input is connected to the trigger output, and the second input to the first register output, 2Q second output of which is connected to the trigger reset input, are entered. respectively with the second group of informational inputs of the block Data entry and the first group of address inputs of the fixed memory unit, the second group of outputs - with the third group of address inputs of the address input block and the second group of address inputs of the permanent memory unit, the third group of outputs is connected to the third group of addressable inputs of the block constant memory is a group of device outputs, a clock input is connected to the output of the first OR element, and information inputs are with the corresponding outputs of a fixed memory block, the fourth group of address inputs of which is connected to the outputs of the bus Rathore, a third group connected to the output of the fourth group of address input unit permanent memory, first and second inputs connected respectively to the input and output device resolution element and a third input is an input device priority. Jsl fie2 J B9 i 0 37 five FIG. cpu.6