JPH01115335U - - Google Patents

Info

Publication number
JPH01115335U
JPH01115335U JP817288U JP817288U JPH01115335U JP H01115335 U JPH01115335 U JP H01115335U JP 817288 U JP817288 U JP 817288U JP 817288 U JP817288 U JP 817288U JP H01115335 U JPH01115335 U JP H01115335U
Authority
JP
Japan
Prior art keywords
circuit
input
eeprom
electronic device
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP817288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP817288U priority Critical patent/JPH01115335U/ja
Publication of JPH01115335U publication Critical patent/JPH01115335U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本案の一実施例を示す回路ブロツク図
、第2図は本案の一実施例の入力回路の自動調整
方法を説明する図、第3図は本案の一実施例の出
力回路の自動調整方法を説明する図である。 1……入力端子、2……A/D変換器、3……
演算処理回路、4……EEPROM、5……D/
A変換器、6……出力端子、7……表示設定回路
Fig. 1 is a circuit block diagram showing an embodiment of the present invention, Fig. 2 is a diagram explaining an automatic adjustment method of an input circuit in an embodiment of the present invention, and Fig. 3 is a diagram illustrating an automatic adjustment method of an output circuit in an embodiment of the present invention. It is a figure explaining an adjustment method. 1...Input terminal, 2...A/D converter, 3...
Arithmetic processing circuit, 4...EEPROM, 5...D/
A converter, 6...output terminal, 7...display setting circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デイジタル演算処理回路と記憶回路及び各種入
出力回路を有する電子装置において、記憶回路に
電気的消去可能な読出し専用半導体メモリ(EE
PROMと略す)を設け、入出力回路の校正用デ
ータをこのEEPROMに書込むことにより装置
の入出力回路の調整を行うことを特徴とする電子
装置。
In an electronic device having a digital arithmetic processing circuit, a memory circuit, and various input/output circuits, electrically erasable read-only semiconductor memory (EE) is used in the memory circuit.
1. An electronic device characterized in that the input/output circuit of the device is adjusted by providing an EEPROM (abbreviated as PROM) and writing calibration data for the input/output circuit into the EEPROM.
JP817288U 1988-01-27 1988-01-27 Pending JPH01115335U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP817288U JPH01115335U (en) 1988-01-27 1988-01-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP817288U JPH01115335U (en) 1988-01-27 1988-01-27

Publications (1)

Publication Number Publication Date
JPH01115335U true JPH01115335U (en) 1989-08-03

Family

ID=31213813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP817288U Pending JPH01115335U (en) 1988-01-27 1988-01-27

Country Status (1)

Country Link
JP (1) JPH01115335U (en)

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