JPS63250758A - Network using microprocessor or the like - Google Patents

Abstract

PURPOSE:To make it possible to connect also an element with slow response time by providing a network with a data temporary holding circuit connected to that held data are outputted to a bus based on an access from a microprocessor or the like. CONSTITUTION:Data on a data bus 3 are acquired and held in the temporary holding circuit 10 for data with a small set-up time at the leading edge part of a data reading signal 4. When an access signal 6 to the circuit 10 is outputted from the microprocessor 1 or the like, the circuit 10 starts to output data held in the data bus 3. Since the microprocessor 1 or the like sufficiently satisfies the set-up time, accurate reading can be attained. Namely, the microprocessor 1 or the like reads out data from an element 2 with a slow response time at first, deletes the read data and then reads out data from the circuit 10 to treat the data as the one obtained from the element 2.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit network using a microprocessor or the like, and more specifically to connecting an element with a slow response time to an Ii2 circuit network using a microprocessor or the like.

2. Description of the Related Art Conventionally, only elements that satisfy the characteristics of the micro-pulse processor's data cutter fl- can be connected to an l111 network using a micro-pulse controller or the like.

Problems to be Solved by the Invention In the above-mentioned circuit network including the conventional blue microprocessor and the like, elements with slow response times could not be connected.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel circuit network that makes it possible to solve the above-mentioned problems inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, a circuit network using a microprocessor or the like according to the present invention acquires and holds data on a data bus using a data read signal from the microprocessor, and
It also has a data temporary holding circuit connected to output held data onto a data bus when accessed by a microprocessor or the like.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to FIG. 1, a microprocessor, etc. has a data bus 3, an address bus 5, and a data read signal line 4.
It has The address bus 5 is connected to a decoder circuit 8, and from the decoder circuit 8, an access signal 7 is sent to the element 2 whose response time is slow depending on the state on the address bus 5.
Alternatively, an access signal 6 to the data temporary holding circuit is output.

The element 2 having a slow response time is connected to a data bus 3 and a data read signal line 4, and is accessed by the microprocessor 1 by an access signal 7. Data temporary holding circuit IOC'i, data bus 3 and data read signal line 4
The held data is temporarily held by the access signal 6 from the microprocessor etc.
The signal is output from the output 9 to the data bus 3.

Next, the operation of misfire II)j will be explained using the second example.

A microprocessor etc. outputs an access signal 7 and a data read signal 4 in order to read the data of the small element 2 for 16 response times. When the microprocessor etc. 1 reads the data on the data bus at the rising edge 21 of the data read signal, the data on the data bus is stored during the setup time 22 before the rising edge 21 and the hold time after the rising edge. time 23
must be determined between. However, since the data output from element 2, which has a slow response time, is slow,
Since the data is determined within the setup time 22, the microprocessor 1 cannot read it accurately. Therefore, the data 24 on the data bus is acquired and held in the data temporary holding circuit 10 with a short set-up time 22 by the rising edge section 21 of the data read signal 4.

Next, the microprocessor, etc., is a data temporary holding circuit.
When the access signal 6 to O is output, the data temporary holding circuit 10 starts outputting the data held on the data bus 3, but in order to sufficiently satisfy the setup time 22 of the microprocessor etc. , microprocessor, etc. 1 is capable of accurate reading.

That is, the microprocessor etc. first reads the data from the element 2 with a slow response time, discards the read data, then reads the data from the data temporary holding circuit 10, and reads the data from the element 2 with a slow response time. J is the data from 2.

In one embodiment shown in FIG.
Although only one I[I! is possible.

As described in detail, according to the present invention, a microprocessor or the like can accurately read data from an element with a slow response time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a time chart illustrating the operation of the embodiment shown in FIG.

Claims (1)

[Claims] It is characterized by having a data temporary holding circuit that acquires and holds data on a data bus in response to a data read signal from a microprocessor, etc., and outputs the held data onto the data bus in response to access from the microprocessor. A circuit network using a microprocessor, etc.