JPS6178350U - - Google Patents
Info
- Publication number
- JPS6178350U JPS6178350U JP16050584U JP16050584U JPS6178350U JP S6178350 U JPS6178350 U JP S6178350U JP 16050584 U JP16050584 U JP 16050584U JP 16050584 U JP16050584 U JP 16050584U JP S6178350 U JPS6178350 U JP S6178350U
- Authority
- JP
- Japan
- Prior art keywords
- operation order
- signal
- cpu
- expansion
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案装置の１実施例の回路ブロツク
図、第２図は同装置の要部回路構成図である。
６…拡張メモリ受け手段（拡張スロツト）、３
…セレクト信号作成手段、８…運用順位指定手段
、９…切換回路手段、１３…リセツト信号発生回
路。
FIG. 1 is a circuit block diagram of one embodiment of the device of the present invention, and FIG. 2 is a circuit diagram of the main part of the device. 6... Expansion memory receiving means (expansion slot), 3
...Select signal generation means, 8. Operation order designation means, 9. Switching circuit means, 13. Reset signal generation circuit.
Claims (1)
メモリ受け手段と、ＣＰＵと、該ＣＰＵのコント
ロールに基づき前記拡張メモリ受け手段に装着さ
れた複数の拡張メモリの運用順位を指定するセレ
クト信号を作成するセレクト信号作成手段と、前
記複数の拡張メモリの運用順位を外部から指定す
るための運用順位指定手段と、該運用順位指定手
段出力と前記セレクト信号とを入力して前記運用
順位指定手段の指定に従う順位で前記セレクト信
号を前記拡張メモリ受け手段に付与する切換回路
手段と、前記運用順位指定手段出力を受け該運用
順位指定手段出力が存在するとき前記ＣＰＵのリ
セツト端子にリセツト信号を付与するリセツト信
号発生回路と、を備えてなる信号処理装置。 A plurality of expansion memory receiving means that allow attachment and detachment of a plurality of expansion memories, a CPU, and a select signal that specifies the operational order of the plurality of expansion memories installed in the expansion memory reception means based on the control of the CPU. a selection signal generation means; an operation order designation means for externally specifying the operation order of the plurality of expanded memories; and inputting the output of the operation order designation means and the select signal to follow the designation of the operation order designation means. switching circuit means for applying the select signal to the expansion memory receiving means in order of priority; and a reset signal for receiving the output of the operation order designation means and applying a reset signal to the reset terminal of the CPU when the output of the operation order designation means is present. A signal processing device comprising a generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16050584U JPS6178350U (en) | 1984-10-24 | 1984-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16050584U JPS6178350U (en) | 1984-10-24 | 1984-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6178350U true JPS6178350U (en) | 1986-05-26 |
Family
ID=30718429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16050584U Pending JPS6178350U (en) | 1984-10-24 | 1984-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6178350U (en) |
-
1984
- 1984-10-24 JP JP16050584U patent/JPS6178350U/ja active Pending
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