JPH0177027U - - Google Patents

Info

Publication number
JPH0177027U
JPH0177027U JP1987171822U JP17182287U JPH0177027U JP H0177027 U JPH0177027 U JP H0177027U JP 1987171822 U JP1987171822 U JP 1987171822U JP 17182287 U JP17182287 U JP 17182287U JP H0177027 U JPH0177027 U JP H0177027U
Authority
JP
Japan
Prior art keywords
memory
delay time
delay line
delay
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987171822U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987171822U priority Critical patent/JPH0177027U/ja
Publication of JPH0177027U publication Critical patent/JPH0177027U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図は本考案の別の実施例を示すブロツク図、
第3図は従来技術の一例を示すブロツク図である
。 1……遅延素子、2……遅延信号線、3……セ
レクタ、4……選択信号線、5……EEPROM
、6……EEPROMデータ線、7……EEPR
OM制御線、8……シリアル−パラレル変換回路
&デコーダ、9……入力端子、10……出力端子
、11……シリアルデータ線、12……シリアル
制御線。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing another embodiment of the present invention;
FIG. 3 is a block diagram showing an example of the prior art. 1... Delay element, 2... Delay signal line, 3... Selector, 4... Selection signal line, 5... EEPROM
, 6...EEPROM data line, 7...EEPR
OM control line, 8... Serial-parallel conversion circuit & decoder, 9... Input terminal, 10... Output terminal, 11... Serial data line, 12... Serial control line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 遅延時間を変更できるように作られたプログラ
マブル遅延線において、電気的に消去/書き込み
が可能なリード・オンリー・メモリを内蔵し該メ
モリの出力によつて前記遅延時間が決まることを
特徴とするプログラマブル遅延線。
A programmable delay line made to be able to change the delay time, characterized in that it has a built-in read-only memory that can be electrically erased/written, and the delay time is determined by the output of the memory. delay line.
JP1987171822U 1987-11-09 1987-11-09 Pending JPH0177027U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987171822U JPH0177027U (en) 1987-11-09 1987-11-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987171822U JPH0177027U (en) 1987-11-09 1987-11-09

Publications (1)

Publication Number Publication Date
JPH0177027U true JPH0177027U (en) 1989-05-24

Family

ID=31463827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987171822U Pending JPH0177027U (en) 1987-11-09 1987-11-09

Country Status (1)

Country Link
JP (1) JPH0177027U (en)

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