JPS6324798U

JPS6324798U -

Info

Publication number: JPS6324798U
Application number: JP11641086U
Authority: JP
Priority date: 1986-07-29
Filing date: 1986-07-29
Publication date: 1988-02-18

Description

[Brief explanation of drawings]

第１図はこの発明による実施例の構成図、第２
図は第１図のタイムチヤート、第３図はメモリ６
のアドレスと設定データ１５の関係説明図。１……制御器、２……カウンタ、３……設定器
、４……加算器、５……セレクタ、６……メモリ
、７……出力回路、８……入力端子、９……出力
端子。 FIG. 1 is a configuration diagram of an embodiment according to the present invention, and FIG.
The diagram shows the time chart in Figure 1, and the diagram in Figure 3 shows the memory 6.
FIG. 3 is an explanatory diagram of the relationship between addresses and setting data 15. 1... Controller, 2... Counter, 3... Setting device, 4... Adder, 5... Selector, 6... Memory, 7... Output circuit, 8... Input terminal, 9... Output terminal .

Claims

[Claims for Utility Model Registration] A counter that counts pulses synchronized with input data, a setter that sets setting data, an adder that adds the counter output and the setter output, and the counter output or the setter output. A memory that uses an adder output as an address input and writes or reads the input data, and an output circuit that samples and stores the memory output with the pulse, and when the memory is in a write mode, the counter output The input data is written to a corresponding address of the memory, and when the memory is set to a read mode, the input data written to the address of the memory corresponding to the output of the adder is read. Shift circuit used.