JPH0289557U - - Google Patents
Info
- Publication number
- JPH0289557U JPH0289557U JP16987588U JP16987588U JPH0289557U JP H0289557 U JPH0289557 U JP H0289557U JP 16987588 U JP16987588 U JP 16987588U JP 16987588 U JP16987588 U JP 16987588U JP H0289557 U JPH0289557 U JP H0289557U
- Authority
- JP
- Japan
- Prior art keywords
- address
- microcomputer
- pull
- prom
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Microcomputers (AREA)
Description
第１図はこの考案の実施例である１チツプマイ
クロコンピユータの主要部の構成を示すブロツク
図である。第２図は同１チツプマイクロコンピユ
ータにおけるＩ／Ｏブロツクに設けられる回路の
例を示す図である。第３図は従来のマイクロコン
ピユータの特定部の回路例を示す図である。
１……ＰＲＯＭセル（ＰＲＯＭ）、２……オプ
シヨンセル、３＋４＋５……アドレス選択回路、
８＋９……トランジスタ回路。
FIG. 1 is a block diagram showing the configuration of the main parts of a one-chip microcomputer that is an embodiment of this invention. FIG. 2 is a diagram showing an example of a circuit provided in an I/O block in the same one-chip microcomputer. FIG. 3 is a diagram showing an example of a circuit of a specific section of a conventional microcomputer. 1...PROM cell (PROM), 2...Option cell, 3+4+5...address selection circuit,
8+9...transistor circuit.
Claims (1)
してアドレスを選択するアドレス選択回路を有す
るマイクロコンピユータにおいて、 前記アドレス選択回路により書き込みアドレス
が選択され、外部より入力されるデータを書き込
むとともに、書き込んだ内容を常時出力するメモ
リセルと、 このメモリセルの出力信号によりオンオフされ
る、プルアツプ抵抗もしくはプルダウン抵抗また
はその他のオプシヨン設定用スイツチを構成する
トランジスタ回路を設けたことを特徴とするマイ
クロコンピユータ。[Claims for Utility Model Registration] In a microcomputer having a writable PROM and an address selection circuit for selecting an address for the PROM, the write address is selected by the address selection circuit and data input from the outside is transmitted. The present invention is characterized by having a memory cell that constantly outputs the written contents as well as writing, and a transistor circuit that constitutes a pull-up resistor, pull-down resistor, or other option setting switch that is turned on and off by the output signal of this memory cell. microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16987588U JPH0289557U (en) | 1988-12-27 | 1988-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16987588U JPH0289557U (en) | 1988-12-27 | 1988-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0289557U true JPH0289557U (en) | 1990-07-16 |
Family
ID=31460320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16987588U Pending JPH0289557U (en) | 1988-12-27 | 1988-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0289557U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61190635A (en) * | 1985-02-19 | 1986-08-25 | Sanyo Electric Co Ltd | Microcomputer |
-
1988
- 1988-12-27 JP JP16987588U patent/JPH0289557U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61190635A (en) * | 1985-02-19 | 1986-08-25 | Sanyo Electric Co Ltd | Microcomputer |
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