JPH03119238U - - Google Patents
Info
- Publication number
- JPH03119238U JPH03119238U JP2715690U JP2715690U JPH03119238U JP H03119238 U JPH03119238 U JP H03119238U JP 2715690 U JP2715690 U JP 2715690U JP 2715690 U JP2715690 U JP 2715690U JP H03119238 U JPH03119238 U JP H03119238U
- Authority
- JP
- Japan
- Prior art keywords
- control
- control memory
- microprogram
- memory
- stores
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 11
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例で、制御記憶の特性
の違うメモリを組み合わせた図、第２図はマイク
ロプログラム制御における一般的な構成例を示す
図、第３図は本考案の一実施例の処理フロー図、
第４図は制御記憶の組み合わせを示す図である。
１……基本制御回路、２……条件回路、３……
シーケンサ、４……制御記憶(1)、５……パイプ
ラインレジスタ、６……制御出力、７……条件入
力信号、８……出力選択、９……クロツク、１０
……アドレス、１１……データ。
Figure 1 shows an embodiment of the present invention, which is a combination of memories with different control memory characteristics, Figure 2 shows a typical configuration example for microprogram control, and Figure 3 shows an embodiment of the present invention. Example processing flow diagram,
FIG. 4 is a diagram showing combinations of control memories. 1... Basic control circuit, 2... Condition circuit, 3...
Sequencer, 4... Control memory (1), 5... Pipeline register, 6... Control output, 7... Condition input signal, 8... Output selection, 9... Clock, 10
...Address, 11...Data.
Claims (1)
ケンサと動作内容を記憶する制御記憶とレーシン
グを防止するパイプラインレジスタより構成する
マイクロプログラム方式の制御装置において、制
御動作を記憶する、制御記憶を、制御記憶(1)、
制御記憶(2)のように複数に分割し、その各々の
制御記憶をＲＯＭとＲＡＭ等の物理的に特性の違
う、制御記憶の使用と回路的に同一の使用に構成
することを構成設定機能により設定可能とし、そ
の設定をマイクロプログラムが認識し、実行開始
時等に構成を切換えることにより、制御対象によ
つて速度、制御記憶容量をダイナミツクに対応可
能にしたことを特徴とするマイクロプログラム制
御装置。 In a microprogram type control device consisting of a sequencer that outputs the address of the microprogram, a control memory that stores the operation contents, and a pipeline register that prevents racing, the control memory that stores the control operation is the control memory (1). ,
A configuration setting function that divides the control memory into multiple parts, such as control memory (2), and configures each control memory to be used in the same circuit as the control memory, which has physically different characteristics such as ROM and RAM. A microprogram control system that is characterized in that the microprogram recognizes the settings and switches the configuration at the start of execution, so that the speed and control storage capacity can be dynamically adjusted depending on the controlled object. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2715690U JPH03119238U (en) | 1990-03-19 | 1990-03-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2715690U JPH03119238U (en) | 1990-03-19 | 1990-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03119238U true JPH03119238U (en) | 1991-12-09 |
Family
ID=31530024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2715690U Pending JPH03119238U (en) | 1990-03-19 | 1990-03-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03119238U (en) |
-
1990
- 1990-03-19 JP JP2715690U patent/JPH03119238U/ja active Pending
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