JPH02116352U - - Google Patents
Info
- Publication number
- JPH02116352U JPH02116352U JP2274189U JP2274189U JPH02116352U JP H02116352 U JPH02116352 U JP H02116352U JP 2274189 U JP2274189 U JP 2274189U JP 2274189 U JP2274189 U JP 2274189U JP H02116352 U JPH02116352 U JP H02116352U
- Authority
- JP
- Japan
- Prior art keywords
- address
- microprocessor
- processing device
- switching means
- arithmetic processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000008707 rearrangement Effects 0.000 description 1
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- Complex Calculations (AREA)
Description
第１図は、本考案の一実施例の演算処理装置の
概略構成を示すブロツク図、第２図は、第１図の
ビツト逆順序並べ替え回路の詳細な構成を示す回
路図、第３図は、本考案の演算処理装置のビツト
逆順序並べ替え動作を説明するための図、第４図
及び第５図は、従来の演算処理装置の問題点を説
明するための図である。
図中、１……ＣＰＵ、２……デコーダ、３……
ＲＯＭ、４……ＲＡＭ、５……ＦＦＴ演算用ＲＡ
Ｍ、６……ビツト逆順序並べ替え回路、７……ノ
オア回路、８……ＣＰＵのデータ・アドレスバス
、９……ＦＦＴ演算用ＲＡＭのアドレス、１０…
…書き込み信号、１１……読し出し信号。
FIG. 1 is a block diagram showing a schematic configuration of an arithmetic processing device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a detailed configuration of the bit reverse order sorting circuit of FIG. 1, and FIG. 1 is a diagram for explaining the bit reverse rearrangement operation of the arithmetic processing device of the present invention, and FIGS. 4 and 5 are diagrams for explaining the problems of the conventional arithmetic processing device. In the figure, 1...CPU, 2...Decoder, 3...
ROM, 4...RAM, 5...RA for FFT calculation
M, 6...Bit reverse order sorting circuit, 7...NOR circuit, 8...CPU data/address bus, 9...FFT operation RAM address, 10...
...Write signal, 11...Read signal.
Claims (1)
において、前記マイクロプロセツサのアドレスの
上位ビツトと下位ビツトを逆順序に並べ替えるア
ドレス切替手段と、該アドレス切替手段の出力を
メモリのアドレスバスに接続すると共に、前記ア
ドレス切替手段の切替えを前記マイクロプロセツ
サのアドレスバスをデコードした信号により行う
制御手段を備えたことを特徴とする演算処理装置
。 In an arithmetic processing device using a general-purpose microprocessor, an address switching means for rearranging upper and lower bits of an address of the microprocessor in reverse order, an output of the address switching means being connected to an address bus of a memory, and . An arithmetic processing device comprising control means for switching the address switching means using a signal decoded from an address bus of the microprocessor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2274189U JPH02116352U (en) | 1989-02-27 | 1989-02-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2274189U JPH02116352U (en) | 1989-02-27 | 1989-02-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02116352U true JPH02116352U (en) | 1990-09-18 |
Family
ID=31241127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2274189U Pending JPH02116352U (en) | 1989-02-27 | 1989-02-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02116352U (en) |
-
1989
- 1989-02-27 JP JP2274189U patent/JPH02116352U/ja active Pending