JPH1185620A - Microcomputer with built-in non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and surely inhibit the third person from reading and writing memory data and to enable read or write in a test mode. SOLUTION: This microcomputer is provided with a security dedicated flash memory 6 for storing end signals 21, 22 and 23 based on plural kinds of write modes in respective prescribed bits, control part 1 for controlling plural kinds of write modes so as to respectively write data from the outside into a flash memory cell 10 and storing the end signals 21, 22 and 23 based on the respective write modes into the respective prescribed bits of the security dedicated flash memory 6 at the time of write end, NOR circuit 7, OR circuit 8 and tristate buffer 9 for inhibiting the write and read of data to the flash memory cell 10 based on the prescribed bits stored in the security dedicated flash memory 6 and a read inhibit cancel signal 42 outputted from the control part 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer with a built-in nonvolatile memory and a one-chip nonvolatile memory, and more particularly to a memory data protection for preventing a third party from reading the memory data of the nonvolatile memory. It is about.

[0002]

2. Description of the Related Art In a one-chip microcomputer incorporating a nonvolatile memory such as a flash memory, for example,
When data such as a program is initially written to the flash memory, one of the following three methods (hereinafter, referred to as
"Selection mode") and a dedicated board for the selection mode.

The selection mode includes, for example, an external PR.
A PROM mode in which data is written by an OM (Programmable Read Only Memory) writer using a dedicated adapter, and a copy mode in which data is copied from an external memory such as a PROM to a built-in flash memory using a dedicated board, There is an on-board write mode (hereinafter, referred to as "serial transfer mode") in which a one-chip microcomputer device having a built-in flash memory mounted on a printed circuit board is connected via a serial port or the like.

In each of the above selection modes, when data is written to the flash memory, a program containing an algorithm corresponding to each selection mode is started, and an identification control circuit for recognizing the CPU, commands related to operations, and the like. Then, the flash memory is accessed via the control register and the like, and writing is performed.

In the selection mode, when it is necessary to keep the written memory data confidential, a function for realizing the confidentiality, that is, a function for inhibiting reading or writing of the memory data is provided. Must be.

The following four functions are known as conventional functions for realizing confidentiality. For example, JP-A-8-1377
No. 57 is disclosed.

When data is written by a PROM writer, a security mode signal is set and a security bit signal is input. As a result, reading or writing is prohibited, and confidentiality of the memory data is maintained. A specific terminal is set when data is written by the PROM writer. This makes it impossible for the PROM writer to write and read again. In writing in the copy mode, a security mode signal is set and a security bit signal is input in the same manner as described above. As a result, reading or writing is prohibited, and security of memory data can be secured. In the serial transfer mode, a password is previously set in a program based on a predetermined format, and this password is input when writing a user program. Thereby, the confidentiality of the memory data is protected.

FIG. 5 shows a specific schematic configuration example for protecting a data memory of a one-chip microcomputer having a built-in nonvolatile memory having the above-described function.

As shown in FIG. 1, the one-chip microcomputer 80 has a built-in flash memory cell 85 as a nonvolatile memory. Here, in order to prohibit reading or writing of memory data in the flash memory cell 85, the output unit 81 sets a mode for prohibiting reading and / or writing of data in the flash memory cell 85. A security mode signal 91 and a security bit signal 92 for setting reading and writing are input.

[0010] These signals 91 and 92 are normally input to the output unit 81 from a specific terminal by a High signal or a Low signal.

The signal output from the output unit 81 is selected by the selection unit 82 and stored in a specific bit of the storage unit 83, and both the security mode signal 91 and the security bit signal 92 are used for reading or writing. When the predetermined signal is not set, the data bus read control circuit 84 can read the memory data content of the flash memory cell 85.

Whether the mode is read-inhibited and / or write-inhibited is read by a security mode signal 91 which determines a mode in which read-inhibition or write-inhibition or both read-out and write-inhibition modes are set.

The security mode signal 91
, And a signal for reading or writing by the security bit signal 92 are inputted, so that the data bus read control circuit 8
4 and a signal for controlling memory reading is output from the storage unit 83 to the mode-specific writing / reading unit 86, thereby reading or writing data to or from the flash memory cell 85. Prohibition is realized.

[0014]

However, the above-mentioned conventional microcomputer with a built-in nonvolatile memory has the following problems as a method for maintaining the security of memory data.

In the case of writing, it is necessary to perform operations such as inputting a security mode signal and a security bit signal at the time of writing, and also to perform operations by terminal setting other than the writing operation such as a necessity of making predetermined settings to specific terminals. Required.

In this case, since the password is fixed, there is a risk that if the password is found, the contents of the memory can be easily read.

By the way, if a non-volatile memory is provided with an absolute confidentiality maintaining mechanism for maintaining confidentiality, for example, when performing maintenance or the like, a serviceman reads out the contents of the memory in the test mode. The inconvenience of being unable to do so occurs.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to simply and reliably prohibit reading and writing of memory data by a third party.
An object of the present invention is to provide a microcomputer with a built-in nonvolatile memory that enables reading or writing in a test mode.

[0019]

According to a first aspect of the present invention, there is provided a microcomputer having a built-in non-volatile memory and comprising one chip of a non-volatile memory. A non-volatile storage means for storing end signals in a plurality of types of write modes in respective predetermined bits, and controlling to write data from the outside to the non-volatile memory in a plurality of types of write modes, and writing the data. Control means for causing the nonvolatile storage means to store an end signal in each write mode in each predetermined bit at the time of termination; predetermined bits stored in the nonvolatile storage means; and read inhibition output from the control means Prohibits writing and reading of data to and from the nonvolatile memory based on the release signal And inhibiting means is characterized in that provided that.

According to the above invention, when writing data to the nonvolatile memory, the control means controls to perform each write of data from the outside into the nonvolatile memory in a plurality of types of write modes. When the writing of the data to the nonvolatile memory is completed, the control unit
At the end of the writing, the non-volatile storage means stores an end signal in each writing mode in each predetermined bit.

Next, the prohibition means writes and reads data to and from the non-volatile memory based on the predetermined bit stored in the non-volatile storage means and a read prohibition release signal output from the control means. Ban.

Therefore, the writing and reading of data to and from the nonvolatile memory can be inhibited by controlling the end signal at the end of writing and the read inhibition release signal output from the control means.

Therefore, a third party cannot write or read data to or from the nonvolatile memory unless the end signal is released or the read inhibition release signal is decoded.

On the other hand, the read prohibition release signal can be instructed by a service person only in a test mode in which reading is possible to maintain the data content of the nonvolatile memory.

As a result, it is possible to provide a microcomputer with a built-in nonvolatile memory that can easily and reliably prohibit the reading and writing of the memory data of a third party while enabling the reading or writing in the test mode.

According to a second aspect of the present invention, there is provided a microcomputer with a built-in nonvolatile memory.
2. The microcomputer with built-in nonvolatile memory according to claim 1, wherein said prohibiting means includes a negative OR circuit, an OR circuit, and an ON / OFF circuit for turning on / off the read and write outputs of said nonvolatile memory. In the negative OR circuit, all the write mode lock signals based on the respective predetermined bits output from the nonvolatile storage means are input, while the OR circuit has the negative OR circuit of the negative OR circuit. An output signal, the read inhibit release signal, and an actual operation mode signal output from the control unit when executing data in the nonvolatile memory are input, and the output of the OR circuit is sent to the ON / OFF circuit. It is characterized by being input.

According to the above invention, all the write mode lock signals based on each predetermined bit output from the non-volatile storage means are input to the negative OR circuit. Therefore, the output of the negative OR circuit becomes a Low signal.

The output of the negative OR circuit is input to the OR circuit, and the OR circuit further outputs a read inhibition release signal and an actual operation output from the control means when executing data in the nonvolatile memory. The mode signal is input.

Here, the read prohibition release signal becomes a High signal only when a service person performs maintenance of the nonvolatile memory, but is usually a Low signal. The actual operation mode signal is also a High signal only when executing data in the nonvolatile memory, and is usually a Low signal.

Accordingly, the output of the OR circuit becomes a Low signal, which is input to the ON / OFF circuit, so that the output of the nonvolatile memory is turned off, and the nonvolatile memory cannot be read or written.

On the other hand, when the service person performs maintenance on the nonvolatile memory, the read inhibition release signal is set to H level.
Since the signal becomes a high signal, the output of the OR circuit becomes a high signal, which is input to the ON / OFF circuit, so that the output of the nonvolatile memory is turned on.
The nonvolatile memory is ready for reading and writing.

As a result, the prohibiting means can be formed with a simple configuration of a negative OR circuit, an OR circuit, and an ON / OFF circuit.

According to a third aspect of the present invention, there is provided a microcomputer with a built-in nonvolatile memory.
3. The microcomputer with built-in nonvolatile memory according to claim 1, wherein the read inhibition release signal is input to a control unit in a test mode in which reading is possible to maintain data contents of the nonvolatile memory. The test means is output from the control means based on a test mode input signal.

According to the above invention, the read inhibition release signal is generated based on the test mode input signal input to the control means in the test mode in which reading is possible to maintain the data contents of the nonvolatile memory. It is output from the control means.

Therefore, a third party cannot operate the read prohibition cancel signal. As a result, it is possible to reliably prohibit a third party from reading or writing data in the nonvolatile memory.

According to a fourth aspect of the present invention, there is provided a microcomputer with a built-in nonvolatile memory,
4. The microcomputer with built-in nonvolatile memory according to claim 3, wherein the test mode input signal is a test mode signal indicating a test mode, and an input formed of a predetermined number of pulses having a predetermined pulse width. On the other hand, when the control means receives an input timing signal having a predetermined pulse width and a predetermined number of pulses within the predetermined timing of the test mode signal, the control means performs a true test. It is characterized in that a read inhibition release signal is output upon recognition of the mode.

According to the above invention, the read prohibition release signal is output from the control means by the test mode input signal input to the control means by the service person. The test mode input signal includes two signals: a test mode signal indicating the test mode, and an input timing signal formed of a predetermined number of pulses having a predetermined pulse width.

Further, the test mode signal and the input timing signal are generated when an input timing signal having a predetermined pulse width and a predetermined number of pulses is input to the control means within a predetermined timing of the test mode signal. , The control means recognizes that the test mode is a true test mode, whereby the control means outputs a read prohibition release signal.

Therefore, even when a service person reads or writes data in the non-volatile memory in the test mode, since a complicated test mode input signal is employed, a third party can meet this condition. It is absolutely impossible to input a test mode input signal and output a read inhibition release signal to the control means.

As a result, it is possible to reliably prohibit a third party from reading or writing data in the nonvolatile memory.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, the one-chip microcomputer according to the present embodiment includes a flash memory cell 10 as a nonvolatile memory and a control unit 1 as a control unit.

The control unit 1 accesses the flash memory cell 10 and has a CPU (Central).
Processing unit 2, built-in algorithm unit 3, control register block 4, and identification control circuit 5.

The algorithm built-in section 3 contains a program for causing the flash memory cell 10 to perform a write operation, a read operation and an erase operation.

Here, the writing operation or the like is performed by selecting one of three methods (hereinafter, referred to as "selection mode"). The three selection modes are PRO
An M (Programmable Read Only Memory) mode, a copy mode, and an on-board write mode (hereinafter, referred to as “serial transfer mode”).

The PROM mode is a mode in which data is written, erased, and read by a PROM writer (not shown) provided externally using a dedicated adapter.

The copy mode is a mode in which data is copied from an external memory such as a PROM to the flash memory cell 10 of a one-chip microcomputer using a dedicated board.

The serial transfer mode is an on-board write mode for performing, via a serial port or the like, a one-chip microcomputer device having a built-in flash memory cell 10 mounted on a printed circuit board as a product.

Next, the above-mentioned control register block 4
The CPU 2 writes data stored in the algorithm built-in unit 3 to access the flash memory cell 10,
This is a register used when executing a read and erase program.

The identification control circuit 5 is a circuit for recognizing commands, data and control data sent from an external PROM writer (not shown) through a PROM writer interface signal 11.

Here, in addition to the above-described PROM writer interface signal 11, a test mode signal 12 and an input timing signal 13 as test mode input signals are input to the control unit 1 from outside. Has become.

On the other hand, the one-chip microcomputer has a security-dedicated flash as a non-volatile storage means used to prohibit reading, writing, and erasing of memory data from a third party to the flash memory cell 10 from the outside. A memory 6 is provided. The security-dedicated flash memory 6 is a non-volatile memory, and is used to prohibit reading data from the flash memory cell 10 when data storage in the flash memory cell 10 in each selection mode is completed. Therefore, PR as an end signal output from the control unit 1
OM mode end signal 21, copy mode end signal 22,
The information of the serial transfer mode end signal 23 is stored.

The security-dedicated flash memory 6 has a PROM mode end signal 21, a copy mode end signal 22, and a serial transfer mode end signal 23.
Memory clear signal 24 for erasing stored information due to
Is input from the control unit 1.

The security flash memory 6 outputs a PROM mode lock signal 31, a copy mode lock signal 32 and a serial transfer mode lock signal 33 as mode lock signals. 32 and 33 are inputted to a negative OR circuit (hereinafter referred to as a “NOR circuit”) 7 and fed back to the control unit 1.

When any one of the PROM mode lock signal 31, the copy mode lock signal 32 and the serial transfer mode lock signal 33 becomes a High signal, the NOR circuit 7 outputs a NOR signal 7a of a Low signal, and outputs the signal 3
This is a circuit that outputs a NOR signal 7a of a High signal when any of 1, 32, and 33 is a Low signal.

Next, the NOR signal 7a is input to an OR circuit (hereinafter, referred to as an "OR circuit") 8, and the OR circuit 8 receives an actual operation mode signal 41 and a read inhibition release signal 42. Is to be entered.

The actual operation mode signal 41 is a signal for instructing reading of the program of the flash memory cell 10 when the control unit 1 executes the program stored in the flash memory cell 10. The read inhibition release signal 42 is used when performing maintenance or the like of a program stored in the flash memory cell 10.
This signal is output from the control unit 1 to the OR circuit 8 when the test mode signal 12 and the input timing signal 13 are input to the control unit 1 when a serviceman reads and writes the contents of the memory for testing. .

In the OR circuit 8, the NOR signal 7a,
When either the actual operation mode signal 41 or the read inhibition release signal 42 becomes a High signal, the OR signal 8a of the High signal is output. When all of the signals 7a, 41, and 42 are the Low signals, the OR signal of the Low signal is output. 8a is output.

The above OR signal 8a is input to a tristate buffer 9 as an ON / OFF circuit.
Thus, when a High signal is input to the tri-state buffer 9, the contents of the memory of the flash memory cell 10 are read, written, and erased.

As a result, the NOR circuit 7, the OR circuit 8, and the tri-state buffer 9 form the inhibiting means.

The security operation in each write selection mode in the one-chip microcomputer having the above configuration will be described. First, the PROM mode will be described.

At the time of a write operation in the PROM mode, first, a PROM writer interface signal 1 output from a PROM writer (not shown) provided outside is provided.
The identification control circuit 5 recognizes the command, data, and control data included in the information. As a result, the processing for the data write command is executed by the control unit 1, and the data is written to the flash memory cell 10.

Then, after the end of writing the last data to the flash memory cell 10, the control unit 1
The mode end signal 21 is output to the security flash memory 6 as a High signal.

At this time, the copy mode end signal 22 and the serial transfer mode end signal 23 are inactive because only the PROM mode is active and executed. As the end signal 23, a low signal is output. Then, the High signal of the PROM mode end signal 21 and the copy mode end signal 2
2 and the Low signal of the serial transfer mode end signal 23 are stored in the security flash memory 6 as respective end signals.

Next, only the PROM mode lock signal 31 from the security flash memory 6 is set to High.
A signal is output, and both the copy mode lock signal 32 and the serial transfer mode lock signal 33 output a Low signal.

These signals 31, 32, and 33 are output from the PROM
Since only the mode lock signal 31 is a High signal output, the NOR signal 7a output from the NOR circuit 7 becomes a Low signal and is input to the OR circuit 8.

On the other hand, one actual operation mode signal 41 of the remaining two input signals from the OR circuit 8 is a signal for activating the user program, and is therefore a Low signal in the write mode.

Also, the read inhibit release signal 42, which is the third input signal to the OR circuit 8, is a signal that becomes an active high signal only when control is performed by setting the test mode. Therefore, in the PROM mode, The read inhibition release signal 42 is a disabled Low signal.

In the OR circuit 8 to which these signals 7a, 41 and 42 are input, the Low signal is output as the OR signal 8a and input to the control gate of the tri-state buffer 9, so that the output of the tri-state buffer 9 is floating. State.

As a result, after writing the data in the flash memory cell 10, it becomes impossible for a third party to read the data in the flash memory cell 10 from the PROM writer.

Further, it becomes impossible to read out the contents of the memory data written in the PROM mode in a copy mode or a serial transfer mode other than the PROM mode.

That is, even if an attempt is made to read data in the copy mode or the serial transfer mode, the PROM mode lock signal 31 from the security flash memory 6 becomes Hi.
gh signal, so that the NOR signal 7a becomes Low.
Signal. As a result, the actual operation mode signal 41
Is always a Low signal in the write selection mode, so that the read inhibit release signal 42 is active High.
This is because the OR signal 8a does not become a High signal unless it becomes an h signal.

In the PROM mode, when newly writing or erasing the flash memory cell 10, the memory clear signal 2 for the PROM mode is used.
4 is output to the security flash memory 6,
After the bit for the PROM mode of the security flash memory 6 is cleared, a write operation in the PROM mode is performed. That is, by clearing the bit for the PROM mode of the security flash memory 6, the PROM mode lock signal 31 becomes L level.
ow signal, whereby the lock signals 31 and 32
Each of 33 becomes a Low signal, and the NOR signal 7a becomes a High signal. Therefore, the OR signal 8a becomes High.
As a result, the tri-state buffer 9 becomes active, and the flash memory cell 10 is ready for writing.

Next, the write selection mode in the copy mode will be described.

In the write operation in the copy mode, the control unit 1 sends a copy mode end signal 22 to the high level after the end of the last data write, as in the PROM mode.
Output as the h signal. At this time, the PROM mode end signal 21 and the serial transfer mode end signal 23 become inactive because the copy mode is executed, so that a Low signal is output, and the security dedicated flash memory 6 ends each of them. The signal is stored.

Next, as output signals of the security flash memory 6, the copy mode lock signal 32 is a high signal, and the PROM mode lock signal 31 is a low signal.
Signal and the serial transfer mode lock signal 33 are Low.
Each is output as a signal.

These signals 31, 32, and 33 are output because the output of the copy mode lock signal 32 is a high signal.
The NOR signal 7a from the NOR circuit 7 is input to the OR circuit 8 as a Low signal.

The remaining two input signals from the OR circuit 8 are
As in the PROM mode, the actual operation mode signal 41 is low.
The read inhibition release signal 42 is a low signal which is disabled in the copy mode.

Accordingly, the OR circuit 8 to which these signals 7a, 41, and 42 are input outputs the OR signal 8a of the Low signal and inputs the signal to the control gate of the tri-state buffer 9. Therefore, the tri-state buffer 9
Is in a floating state, and the data of the flash memory cell 10 cannot be output onto the data bus.

The memory data written in the copy mode can be read in a PROM mode other than the copy mode or in a serial transfer mode.
This is impossible for the same reason as in the OM mode.

When writing or erasing data to or from the flash memory cell 10 in this copy mode, a memory clear signal 24 is output from the control unit 1 and the bit for the copy mode of the security flash memory 6 is set. After clearing, a write operation in the copy mode is performed.

Finally, the write selection mode in the serial transfer mode will be described.

Also in the serial transfer mode, the controller 1 outputs the serial transfer mode end signal 23 as a High signal after the end of the last data writing, as described above. At this time, the PROM mode end signal 21
Since the serial transfer mode is active and executed, the copy mode end signal 22 becomes inactive and a low signal is output, and the end signals 21, 22 and 23 are stored in the security flash memory 6. .

Then, the serial transfer mode lock signal 33 is output from the security flash memory 6 to Hi.
The gh signal, the PROM mode lock signal 31 is output as a Low signal, and the copy mode lock signal 32 is output as a Low signal.

Since the output of the serial transfer mode lock signal 33 is a High signal, the NOR signal 7a, which is the output of the NOR circuit 7,
Is input to the OR circuit 8 as a Low signal.

The remaining two input signals to the OR circuit 8 are, as in the PROM mode and the copy mode, the actual operation mode signal 41 is a Low signal, and the read inhibition release signal 42 is also in the serial transfer mode. This is a disabled Low signal.

Therefore, the OR circuit 8 to which these signals 7a, 41, and 42 are input outputs the Low signal as the OR signal 8a and inputs it to the control gate of the tri-state buffer 9. For this reason, the output of the tri-state buffer 9 is in a floating state, and the data of the flash memory cell 10 cannot be output on the data bus.

By the above operation, reading and writing of the memory data of the flash memory cell 10 are prohibited in any of the write selection modes.

On the other hand, in the present embodiment, the test mode signal 12 and the input timing signal 13 are assigned to specific terminals as the only operation to release the read prohibition state of the memory data contents in each write selection mode. A test mode for inputting necessary signals is provided.
Therefore, at the time of maintenance of the program stored in the flash memory cell 10, the operation shifts from the test mode state to the read prohibition release routine by the activation of the built-in algorithm unit 3, and the operation is performed.

The operation in the read prohibition releasing routine will be described with reference to the timing chart of FIG. 2 and the flowchart of FIG.

First, as shown in FIG. 2, in the present embodiment, if the input signal TESTt of the test mode signal 12 recognized as the test mode and the input timing signal 13 of the pulse Tt are not input simultaneously, Algorithm built-in section 3 with built-in read prohibition release routine
Is not started.

When the input signal TESTt of the test mode signal 12 and the input timing signal 13 of the pulse Tt are input simultaneously, the test mode state is recognized by the control unit 1 and The process proceeds to the read inhibition release routine.

In the read prohibition releasing routine, as shown in the flowchart of FIG. 3, first, the write mode is determined (S1).

Next, the number and pulse width of the input timing signals 13 in each of the High signal in the timing At period, the Low signal in the timing Bt period, and the High signal in the timing Ct period in the test mode signal 12 are simultaneously monitored. You.

Specifically, it is determined whether or not there are two pulses of the pulse width at in the input timing signal 13 in the High signal in the timing At period in the test mode signal 12 (S2).

If it is determined that the input signal is other than the two pulses, the process returns to S1 at that point and the test mode signal 12 and the input timing signal 13 must be set again.

Similarly, it is determined whether there are three pulses of the pulse width at in the input timing signal 13 in the Low signal of the timing Bt period in the test mode signal 12 (S3). It is determined whether there are four High pulses of the pulse width at in the input timing signal 13 in the High signal of the timing Ct period in (S).
4).

If the High pulse having the pulse width at as the input timing signal 13 does not enter the predetermined number of times as the input timing signal 13 within the predetermined period also in the timing Bt period and the timing Ct period, the process returns to S1 and continues forever. Reading of memory data by the read prohibition release routine becomes impossible.

As described above, the state of each write selection mode, the state of the test mode signal 12 within a predetermined period, and the input timing signal 13 are analyzed to determine the test mode state. PROM mode lock signal 3 which is the output signal of
1. Any one of the High signal of the copy mode lock signal 32 and the serial transfer mode lock signal 33 is determined,
At the same time that the bit for each applicable write mode is cleared by the memory clear signal 24, control for setting the read inhibition release signal 42 to a High signal is performed (S5).

As a result, a Low signal is output as the lock signal of the corresponding write selection mode, and the NOR signal 7a becomes a High signal. The actual operation mode signal 41 is a low signal as an inactive state,
In addition, the read inhibition release signal 42 is a High signal.
Therefore, the OR signal 8a output from the OR circuit 8 is high.
It becomes an high signal. Therefore, the control gate of the tri-state buffer 9 becomes active, so that the contents of the memory data can be read.

Finally, as shown in the flowchart of the read prohibition routine in FIG. 4, after determining which write selection mode is applicable (S11 to S11).
13) The High signal is output again as the end signal, and the Low signal is output as the read inhibition release signal 42 (S14).

As a result, the actual operation mode signal 41 in the test mode is a low signal because it is inactive, and the signals 7a and 41 input to the OR circuit 8 are output.
Since all of the signals 42 are Low signals, the OR circuit 8 outputs the OR signal 8a of the Low signal. For this reason,
The tri-state buffer 9 enters a floating state, so that reading of memory data from the flash memory cell 10 becomes impossible.

In this embodiment, in S5 of the read prohibition release routine shown in the flowchart of FIG. 3, the bit for each of the corresponding write modes of the security flash memory 6 is cleared by the memory clear signal 24. However, this is not absolutely necessary. This is because at least one of the three input signals input to the OR circuit 8 is High.
If the signal becomes a signal, the OR signal 8a becomes a High signal and the tristate buffer 9 becomes a readable state. Therefore, if the read inhibition release signal 42 is a High signal, the condition is satisfied.

However, as a practical matter, it is preferable to know what the final write selection mode is. Therefore, in this embodiment, the bit for each corresponding write mode of the security flash memory 6 is set. Is to leave one of the selection modes.

As described above, in each write selection mode, a data write end signal is stored in the security flash memory 6, and the lock signal of each selection mode output from the security flash memory 6 and the memory in the test mode are used. After the last data of the write selection mode is written, the read operation can be automatically inhibited after the last data in the write selection mode has been written. Since the identification is performed by shifting to the read prohibition release routine, it becomes impossible for another person to easily read the contents of the memory data.

Therefore, the memory data read function and read prohibition are performed based on the timing and the number of signals input in the test mode in order to prevent illegal release, rather than merely setting the security mode, so that security can be ensured.

As described above, in the microcomputer with a built-in nonvolatile memory according to the present embodiment, when writing data to the flash memory cell 10, the control unit 1 writes a plurality of types of data from the outside to the flash memory cell 10. Control is performed to perform each write in a mode, that is, a PROM mode, a copy mode, or a serial transfer mode. When the writing of the data to the flash memory cell 10 is completed, the control unit 1 sends the data to the security flash memory 6 at the end of the writing.
An end signal in each write mode is stored in each predetermined bit.

Next, a NOR circuit 7 as a prohibiting means,
The OR circuit 8 and the tri-state buffer 9 are provided with a predetermined bit stored in the dedicated security flash memory 6 and a read inhibition release signal 42 output from the control unit 1.
And writing and reading of data to and from the flash memory cell 10 are prohibited.

Therefore, the writing and reading of data to and from the security flash memory 6 are output from the control unit 1 and the PROM mode end signal 21, the copy mode end signal 22 and the serial transfer mode end signal 23 at the end of writing. By controlling the read prohibition release signal 42, the prohibition can be achieved.

For this reason, the third party sends the end signal 21.
22 or 23 or read inhibit release signal 42
, Data cannot be written to or read from the flash memory cell 10.

On the other hand, the read prohibition release signal 42 can be a signal that can be input by a serviceman only in the test mode in which reading is possible to maintain the data content of the flash memory cell 10.

As a result, it is possible to provide a microcomputer with a built-in nonvolatile memory that can easily and reliably prohibit reading and writing of memory data by a third party, while enabling reading or writing in the test mode.

Further, in the microcomputer with a built-in nonvolatile memory according to the present embodiment, the inhibiting means includes a NOR circuit 7, an OR circuit 8, and a tri-state buffer 9 for turning on / off the read / write output of the flash memory cell 10. Consists of

Therefore, the NOR circuit 7 has all the write mode lock signals based on each predetermined bit outputted from the security flash memory 6, that is, the PROM mode lock signal 31, the copy mode lock signal 32 and the serial transfer mode lock signal 33. Is entered,
One of the write modes is a High signal, and the output signal of the NOR circuit 7 is NO.
The R signal 7a becomes a Low signal.

The NOR signal 7a, which is the output of the NOR circuit 7, is input to the OR circuit 8, and the OR circuit 8 further supplies the read inhibit release signal 42 and the control unit when executing the data of the flash memory cell 10. 1 is input.

Here, the read prohibition release signal 42 becomes a High signal only when a service person performs maintenance on the flash memory cell 10, but is normally Low.
Signal. The actual operation mode signal 41 also becomes a high signal only when data of the flash memory cell 10 is executed, and is usually a low signal.

Therefore, the output of the OR circuit 8 becomes a Low signal, which is input to the tri-state buffer 9, so that the output of the flash memory cell 10 is turned off and the flash memory cell 10 cannot be read or written. .

On the other hand, when the service person performs maintenance on the flash memory cell 10, the read inhibition release signal 42 becomes a High signal.
The OR signal 8a output from the OR circuit 8 becomes a High signal, which is input to the tri-state buffer 9, so that the output of the flash memory cell 10 is turned on,
The flash memory cell 10 is ready for reading and writing.

As a result, the prohibiting means is changed to the NOR circuit 7, O
It can be formed with a simple configuration of the R circuit 8 and the tri-state buffer 9.

In the microcomputer with a built-in nonvolatile memory according to the present embodiment, the read inhibit release signal 42
Is controlled based on a test mode signal 12 and an input timing signal 13, which are test mode input signals input to the control unit 1, in a test mode in which data can be read out for maintenance of the data content of the flash memory cell 10. This is output from the unit 1.

Therefore, the read prohibition cancel signal 42 cannot be operated by a third party. As a result, it is possible to reliably prohibit a third party from reading or writing data in the flash memory cell 10.

In the microcomputer with a built-in nonvolatile memory according to the present embodiment, the read inhibit release signal 42
Is output from the control unit 1 by a test mode input signal input to the control unit 1 by a serviceman. Also,
The test mode input signal includes two signals: a test mode signal 12 indicating the test mode, and an input timing signal 13 formed of a predetermined number of pulses having a predetermined pulse width at.

The test mode signal 12 and the input timing signal 13 are input timing signals having a predetermined pulse width at and a predetermined number of pulses within a predetermined timing At, Bt, Ct period of the test mode signal 12. When 13 is input to the control unit 1, the control unit 1 recognizes that the test mode is a true test mode,
As a result, the control unit 1 outputs the read inhibition release signal 42.

Therefore, even when a service person reads or writes data in the flash memory cell 10 in the test mode, the test mode signal 12 and the input timing signal 13 which are such complicated test mode input signals are employed. Therefore, the third party inputs the test mode signal 12 and the input timing signal 13 that meet this condition, and sends the read inhibition release signal 42 to the control unit 1.
Is absolutely impossible.

As a result, it is possible to reliably prohibit a third party from reading or writing data in the flash memory cell 10.

[0126]

As described above, the microcomputer with built-in nonvolatile memory according to the first aspect of the present invention has a nonvolatile storage means for storing end signals in a plurality of types of write modes in respective predetermined bits, and Control means for controlling the writing of data to the nonvolatile memory in a plurality of types of write modes, and for storing, at the end of the write, the nonvolatile storage means with an end signal in each write mode in each predetermined bit Prohibiting means for prohibiting writing and reading of data to and from the non-volatile memory based on a predetermined bit stored in the non-volatile storage means and a read prohibition release signal output from the control means. Is what it is.

Therefore, writing and reading of data to and from the non-volatile memory are performed by an end signal at the end of writing, and
By controlling the read prohibition release signal output from the control means, the prohibition can be achieved.

Therefore, a third party cannot write or read data to or from the nonvolatile memory unless the end signal is released or the read inhibition release signal is decoded.

On the other hand, the read prohibition release signal can be instructed by a service person only in the test mode in which reading is possible to maintain the data content of the nonvolatile memory.

As a result, it is possible to provide a microcomputer with a built-in nonvolatile memory that can easily and reliably prohibit reading and writing of memory data by a third party while enabling reading or writing in the test mode. To play.

The microcomputer with built-in nonvolatile memory according to the second aspect of the present invention is the microcomputer with built-in nonvolatile memory according to claim 1 as described above.
The prohibiting means turns on the negative OR circuit, the OR circuit, and the read and write outputs of the nonvolatile memory.
And an ON / OFF circuit for turning on / off all the write mode lock signals based on each predetermined bit output from the non-volatile storage means. Receives the output signal of the negative OR circuit, the read inhibit release signal, and the actual operation mode signal output from the control means when executing data in the nonvolatile memory; The output is input to the ON / OFF circuit.

Therefore, there is an effect that the inhibiting means can be formed with a simple configuration of a negative OR circuit, an OR circuit and an ON / OFF circuit.

The microcomputer with built-in nonvolatile memory according to the third aspect of the present invention is the microcomputer with built-in non-volatile memory according to claim 1 or 2, wherein the read-inhibition canceling signal is transmitted to the nonvolatile memory. The data is output from the control means based on a test mode input signal input to the control means in a test mode in which reading is possible to maintain the data contents.

Therefore, the read prohibition cancel signal cannot be operated by a third party. As a result, it is possible to reliably prevent a third party from reading or writing data in the nonvolatile memory.

According to a fourth aspect of the present invention, there is provided the microcomputer with the built-in nonvolatile memory according to the third aspect of the present invention.
The test mode input signal includes a test mode signal indicating a test mode, and an input timing signal formed of a predetermined number of pulses having a predetermined pulse width. Within a predetermined timing of the signal, when an input timing signal having a predetermined pulse width and a predetermined number of pulses is input to the control unit, the control unit recognizes that the test mode is a true test mode and generates a read inhibition release signal. Output.

Therefore, even when a service person reads or writes data in the non-volatile memory in the test mode, since a complicated test mode input signal is employed, a third party can meet this condition. It is absolutely impossible to input a matching test mode input signal and cause the control means to output a read inhibition release signal.

As a result, there is an effect that a third party can be reliably prohibited from reading or writing data in the nonvolatile memory.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a microcomputer with a built-in nonvolatile memory according to the present invention.

FIG. 2 is a timing chart showing a relationship between a test mode signal and an input timing signal in the microcomputer with a built-in nonvolatile memory.

FIG. 3 is a flowchart showing a control operation of a read prohibition release routine in the microcomputer with built-in nonvolatile memory.

FIG. 4 is a flowchart showing a control operation of a read prohibition routine in the microcomputer with built-in nonvolatile memory.

FIG. 5 is a configuration diagram showing a conventional microcomputer with built-in nonvolatile memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Control part (control means) 6 Flash memory for exclusive use of security (nonvolatile storage means) 7 NOR circuit (negative OR circuit, inhibition means) 7a NOR signal 8 OR circuit (OR circuit, inhibition means) 8a OR signal 9 tristate Buffer (ON / OFF circuit, prohibiting means) 10 Flash memory cell (non-volatile memory) 12 Test mode signal (Test mode input signal) 13 Input timing signal (Test mode input signal) 21 PROM mode end signal (End signal) 22 Copy Mode end signal (end signal) 23 Serial transfer mode end signal (end signal) 24 Memory clear signal 31 PROM mode lock signal (mode lock signal) 32 Copy mode lock signal (mode lock signal) 33 Serial transfer mode lock signal (mode lock) Signal) 41 Actual operation mode signal 42 Read inhibit release signal

Claims (4)

[Claims] 1. A microcomputer having a built-in nonvolatile memory and comprising one chip of nonvolatile memory, comprising: a nonvolatile storage means for storing end signals in a plurality of types of write modes in predetermined bits; Control means for controlling each write in a plurality of types of write modes of data to the non-volatile memory, and, when the write is completed, causing the nonvolatile storage means to store an end signal in each write mode in each predetermined bit. Prohibiting means for prohibiting writing and reading of data to and from the non-volatile memory based on a predetermined bit stored in the non-volatile storage means and a read prohibition release signal output from the control means; A microcomputer with a built-in nonvolatile memory. 2. The above-mentioned prohibiting means comprises a negative OR circuit, an OR circuit, and an ON / OFF circuit for turning ON / OFF the read and write outputs of the nonvolatile memory. Receives all the write mode lock signals based on each predetermined bit output from the nonvolatile storage means, while the OR circuit outputs an output signal of the negative OR circuit,
The read inhibit release signal and the actual operation mode signal output from the control means when executing the data in the nonvolatile memory are input, and the output of the OR circuit is input to the ON / OFF circuit. The microcomputer with a built-in nonvolatile memory according to claim 1. 3. The control means according to claim 2, wherein said read inhibit release signal is supplied to said control means based on a test mode input signal inputted to said control means in a test mode in which reading is possible to maintain data contents of said nonvolatile memory. The microcomputer with a built-in nonvolatile memory according to claim 1, wherein the microcomputer outputs the data. 4. The test mode input signal comprises: a test mode signal indicating a test mode; and an input timing signal formed of a predetermined number of pulses having a predetermined pulse width. The means recognizes that the test mode is a true test mode when an input timing signal having a predetermined pulse width and a predetermined number of pulses is input to the control means within a predetermined timing of the test mode signal. And outputting a read prohibition cancel signal.
A microcomputer with a built-in nonvolatile memory as described in the above.