KR940006823B1 - Circuit for protecting memory write - Google Patents

Abstract

The circuit improves the data reliability and the memory maintenance function adding the memory writting protection facility. The circuit comprises: a write protection memory (10B) outputting the control signal from the memory protection unit; a microprocessor (10A) generating the address signal when the processor (10A) accesses the D-RAM memory unit (70A); a bus control unit (80A) controlling the output data of the microprocessor (10A); and a write enable unit (10C) outputting the write control unit outputs the write control signal.

Description

Memory write protection circuit

1 is a conventional circuit diagram.

2 is a schematic view according to the invention.

3 is a memory write protection address allocation map according to the present invention.

4 is a detailed circuit diagram of FIG. 2 in accordance with the present invention.

The present invention relates to a memory write protection circuit in a communication system, and more particularly, to a circuit for reliability of memory data and efficient management of a memory.

In general, it is common for a processor to store data in memory and use it as an intention / disabled device through an input / output device.

1 is a block diagram of the prior art, and most of the current methods are used. The microprocessor 10A controls each part of the circuit according to an input command by a program, the data transceiver 20A transmits and receives data bidirectionally, and the address latch 30A latches the address signal according to the address cycle. The D-RAM address multiplexer 40A multiplexes the ROW address column addresses of the D-RAM memory section 70A, and the address decoder 50A accesses the D-RAM memory section 70A. To control the chip enable (RAS, CAS signal generation), the D-RAM controller 60A controls the chip enable signal of the D-RAM memory unit 70A (RAS, CAS), D-RAM The memory unit 70A stores data, and the bus control unit 80A is configured to generate a microprocessor 10A command signal.

Looking at the operation relationship of Figure 1 as follows. The method used in Figure 1 shows how most of the current methods used to read and write data in memory.

When reading data from the first memory, the microprocessor 10A first takes out an instruction from the memory to read the memory data, and then executes an address through the address bus of the microprocessor 10A. Will pass through. The signal passing through the address decoder 50A generates the RAS and CAS signals capable of enabling the chip of the D-RAM memory unit 70A through the D-RAM control unit 60A. The D-RAM memory unit 70A distinguishes a row address and a column address through an address latch 30A and a D-RAM address multiplexer 40A to access an arbitrary area of the D-RAM memory unit 70A. Next, the microprocessor 10A transmits a memory read signal to the D-RAM memory unit 70A after a predetermined timing passes. At this time, the data of the memory is transferred to the microprocessor 10A through the data bus.

When the second memory data writing cycle is executed by the microprocessor 10A to write the memory data, the same operation as the address read operation is performed first, and then the microprocessor 10A replaces the memory read signal after a predetermined timing. When a memory write signal is sent to the D-RAM memory unit 70A, and data is loaded onto the data bus at the same time, data is written to a desired memory area. When the microprocessor 10A transmits the read and write status signals S0-S2 to the bus control unit 80A, the memory control unit reads and writes the signals to the bus control unit 80A. You will create a command ring to identify the cycles.

For this reason, conventionally assuming that important data exists in a certain area later, there is an area where data change should not occur when data is stored in the memory. In this case, since the memory write protection function is not implemented in the conventional technology, there is no way to preserve the existing important data when writing data to the memory. Therefore, it is necessary to maintain and efficiently manage important data stored in the memory. do.

Accordingly, an object of the present invention is to provide a circuit having data reliability and memory management function by adding a memory write protection function to allow storage when data is stored in the memory.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram according to the present invention, in which the microprocessor 10A accesses the D-RAM memory unit 70A and write-protects from an address signal and a memory protection control signal generated from the microprocessor 10A. The write protection memory 10B for generating a control signal, the bus control unit 80A for bus control of the output data of the microprocessor 10A, the output of the write protection memory 10B and the bus control unit 80A All of the outputs are composed of the write enable control means 10C which generates the write control signal only when the write control signal of the D-RAM memory unit 70A is generated.

3 is a memory write protection address map diagram according to the present invention.

4 is a detailed circuit diagram of an embodiment according to the present invention, in which the write-protect memory 10B is stored as data bus information for determining whether the memory is write-protected, and the processor control register 20B: for controlling the processor. Stores data information bits, logic controller 1 30B provides an enable signal to memory write-protect memory, logic controller 2 40B provides a data write signal to memory write-protect memory 10B, and logic controller 3 (50B) provides a memory protection vibration (MPV) data bit signal to the processor control register 20B while providing an unmasked interrupt (NMi) signal to the processor 10A.

Logic control unit 4 (60B) cancels the write cycle signal when the write prohibition is programmed in the area of D-RAM memory unit 70A, and logic control unit 5 (70B) cancels the D-RAM memory unit 70A data. When reading, it is controlled regardless of the memory write protection function.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 2 through 4, and the memory write-protect memory structure has a maximum size of the D-RAM memory unit 70A as 1M bytes as shown in FIG. In the write-protect memory map 10B, the write-protect program data bits may be stored in units of 1K bytes of the D-RAM memory unit 70A. If the data bit of the memory write-protect memory 10B is " 0 ", writing data to the D-RAM memory unit 70A is protected. If the data bit is set to " 1 ", the data can be written. Do.

In programming the write-protect memory 10B, when programming data to the write-protect memory 10B in FIG. 4, first, the "PROG" bit of the processor control register 20B is set to "1", and the "MPI" bit is set to "." 0 ", respectively, at this time, enabling write protection memory 10B with logic control unit 1 (30A), and processor control register (20B) having a bit of " PROG " The RAS and CAS signals are not provided through the D-RAM control unit 60A so as not to access the unit 70A. Therefore, the D-RAM memory unit 70A is not in a write mode, but the write-protect memory 10B is switched to a mode in which data bits are stored. In this mode, the microprocessor 10A transmits an address for determining whether the area is write protected (prohibited) to the write protection memory 10B via the address bus in this mode. The programming is completed by loading the data onto the data bus (D0 bit valid) and providing the write signal so that the logic controller 2 40B can store the data in the write-protect memory 10B. In this way, if all the data bits for determining whether to write-protect all the areas of the D-RAM memory unit 70A are programmed in the write-protect data 10B area, the write cycle of the D-RAM memory unit 70A will be described later. Determine whether to store data in the D-RAM memory section 70A according to the contents of the write protection memory 10B.

To cancel the memory write protection function, if the memory write protection function is not used in FIG. 4, that is, when used with the prior art (FIG. 1), first set the bit of the "MPI" in the processor control register 20B to "1". By setting, the write-protect memory 10B is disabled through the logic controller 1 30B. This cancels the memory write protection function even when data is stored in the D-RAM memory unit 70A in the future, so that an unmasked interrupt NMi does not occur.

Referring to the memory write protection operation relationship, the memory write cycle has described the partial description of the memory write protection circuit based on FIG. 3 and FIG. 4 as described above. The operation will be described in detail.

First, a few assumptions are made prior to describing the circuit operation.

As described in the programming of the first write-protect memory 10B, the data bits (0: write prohibited, 1: write enabled) for determining whether to prevent the memory write are written for each memory area of the 1-byte unit of the D-RAM memory unit 70A. Programming to be stored in the preventive memory 10B is completed. Program the data bits as shown in Figure 3.

Secondly, the "PROG" bit and the "MPI" bit in the processor control register 20B are set to "0" to enable the memory write protection function.

It is assumed that the specific area of the third D-RAM memory unit 70A is memory write inhibited (prevented) so that data information is stored in the write protect memory 10B. In addition, assuming that the microprocessor 10A performs a write instruction for storing some data in the specific area, the operation is as follows.

First, when the microprocessor 10A performs a memory write cycle, the memory address of the specific area is loaded on the address bus. The address reaches the address terminal of the D-RAM memory section 70A at the same time as the (memory) write protection memory 10B, which is connected to the RAS of the D-RAM memory section 70A via the D-RAM control section 60A. The CAS signal is provided to enable memory write. At this time, the microprocessor 10A loads data on the data bus in the next cycle, the data cycle, and generates a memory write signal through the bus controller 80A. This means that the contents of the write protection memory 10B of the corresponding area are output through the logic control unit 1 30B through the write protection memory 10B output terminal. Since the output data is assumed to be a memory write prohibition signal of a specific region of the D-RAM memory unit 70A, it is output as "0". This output signal is stored in the "MPV" bit of the processor control register 20B through logic control unit 3 (50B) and also transmitted to the unmasked interrupt (NMi) terminal of the microprocessor 10A. At this time, the microprocessor 10A continues to hold an unmasked interrupt (NMi) request until the current memory write cycle is completed. At this time, the microprocessor 10A does not process the non-masked interrupt NMi until the instruction cycle is completed.

On the other hand, since the microprocessor 10A transmits a write status signal to the bus controller 80A because data was previously loaded on the data bus in the data cycle, the memory write command (/ MWR) is transmitted to the D-RAM memory unit. When passed to the write enable (/ WE) terminal of 70A, data is written to the memory. However, the write protection memory 10B output signal transmits the memory write command status of the microprocessor 10A to the bus control unit 80A, and is combined with the point in time at which the command (/ MWR) output signal of the bus control unit 80A is sampled. Through the logic control unit 4 (60B) and logic control unit 5 (70B), the write enable (/ WE) terminal of the D-RAM memory unit 70A is completed before the microprocessor 10A completes the memory write cycle. Disabling prevents data on the data bus from being written to memory. At this time, the microprocessor 10A completes a memory write cycle and performs processing for a previously registered non-masked interrupt request. This interrupt NMi is jumped to the microprocessor 10A where a predetermined interrupt service processing routine is located. The service processing routine software can read the " MPV " bit of the processor control register 20B and analyze the memory write vibration (MPV) signal information indicating that a memory write has occurred in the processor memory write prohibited area. Therefore, according to the "MPV" bit information, software must be prepared for the microprocessor 10A to perform appropriate processing.

Memory Read Cycle The memory read cycle is simple. It operates in the same manner as the prior art (FIG. 1). Since the memory write protection function (Fig. 4), the memory read cycle is not related to the memory write protection function. This is the same as that of the prior art (Fig. 7) by providing the D-RAM memory unit 70A with a signal that is not related to the memory write function through the logic control unit 5 (70B).

As described above, by implementing the memory write-protection circuit of the present invention, when data is written into the memory, no data change should occur, but it is possible to efficiently manage the reliability and memory of the data by providing a write prohibition signal in an important area. .

Therefore, in general, it is obvious that a D-RAM memory is a memory that can be read and written. However, in order to preserve a certain area of data if necessary, the area should be read only and the data of the area should not be changed. Therefore, in the present invention, by adding the function, it can be controlled by software. If the data is not reliable while the software is running, the results are not as intended by the user. As described above, it is a major advantage of the present invention that the data can be securely protected, a write protection function of a memory area can be provided according to a user's use, and the memory can be efficiently managed and maintained.

Claims (1)

In the memory write protection circuit, the microprocessor 10A generates a write protection control signal from the memory protection control signal and the address signal generated from the microprocessor 10A in accessing the D-RAM memory unit 70A. The write control memory 10B, the bus control unit 80A for bus control of the output data of the microprocessor 10A, the output of the write protection memory 10B, and the output of the bus control unit 80A are all the D. And a write enable control means (10C) which generates a write control signal only at one time of the write control signal of the RAM memory unit (70A).