JP2732052B2 - Control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a control circuit constituted by a CPU in a control device. [Prior Art] Conventionally, this type of control device has been subjected to final adjustment in which data to be adjusted for each control device is set in a RAM (random access memory) at the time of shipment from a manufacturing factory (software / software). Called volume). Therefore, the software volume value was programmed not to be initialized by software so that the value would not change even if the CPU was reset. Further, all the write operations of the CPU are enabled for the entire memory space of the RAM. In this type of control circuit, the control is performed by a program executed by the CPU. Therefore, the control is performed by electrostatic noise (for example, generated when a human body comes into contact with the control device) applied to the control device. The CPU erroneously executes a program due to noise jumped into the control circuit unit, writes an erroneous value of a soft volume to the RAM, and results in a malfunction (runaway) of a control device. The equipment could be fatally damaged. For this reason, conventionally, a detection circuit that monitors the execution of the software has been adopted, and if a runaway of the software is detected, a reset signal is given to a CPU used in the control circuit to initialize the software. By doing so, the normal operation was resumed. FIG. 5 shows a block diagram of an example of this type of conventional control circuit. In the figure, 201 is a CPU for controlling the control device, 205
Is a ROM (read only memory) in which an execution program is written, 206 is a RAM for holding data, 207 is an I / O (interface) device such as a display and a clutch connected to a control device, and And 203, an address bus from the CPU 201, 204, a data bus, and 202, an address decoder that decodes each address of the address bus 203 and allocates each address to the ROM 205, the RAM 206, and the I / O device. 208 is a software runaway detection circuit, 209 is a pulse output at regular intervals during normal operation of the software, 210
Is a reset signal output from the runaway detection circuit 208. FIG. 6 shows a sequence flowchart of the above program. That is, in step S1, it is determined whether or not the soft volume is set, and if it is set, the value is set (step S2). If not set, the control device is initialized in step S3, and in step S4,
Pulses 209 at regular intervals are output, and the process of the control device is performed in step S5, and the process returns to step S4. If the program is operating normally, the signal 209 is applied from the CPU 201 to the runaway detection circuit 208 as described above. Runaway detection circuit 208 does not output reset signal 210 while the pulse is being applied. FIG. 7 shows a waveform timing chart of the pulse 209 and the reset signal 210 when the software runs away. That is, until time t ₁ , the software performs a normal operation, and at this time t ₁ , the software runs away due to electrostatic noise or the like, and stops outputting the pulse 209.
Thus, over time interval T, and initialize outputs a reset signal 210 at time t _2, shows how to resume normal operation from the time point t _3. [Problems to be Solved by the Invention] As described above, the control device returns to the normal operation again, however, during the time interval T, the CPU 201
There is a possibility that erroneous data is written to the RAM 206 in the soft volume area. That is, in the above-described conventional example, there is a danger that erroneous data is written in the soft volume area due to runaway of software. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the related art, and has a control to prohibit an operation of writing erroneous data to a soft volume area until a control device is reset at the time of the software runaway. The purpose is to provide circuits. [Means for Solving the Problems] For this reason, in the present invention, in a control circuit for writing data to a rewritable memory, an address for transferring an address data designating an address for writing data to the memory is provided. A bus, a data bus for transferring data to be written to the memory, detection means for detecting that the control circuit has designated a specific address of the memory via the address bus, and write control by the control circuit It can be driven independently of the
A switch for outputting a signal prohibiting writing of data to the specific address via the data bus when the detection unit detects that the specific address has been designated, thereby achieving the object. Is to achieve. [Operation] With the above-described configuration, even if an erroneous write operation to the soft volume area occurs due to runaway due to noise or the like of the software for controlling the device, the contents of the storage means may be changed. Is suppressed. Examples Hereinafter, the present invention will be described based on examples. FIG. 1 is a block diagram showing one embodiment of a control circuit according to the present invention. (Configuration) 101 is an 8-bit CPU, 102 is an address decoder,
This is for assigning (addressing) each address to the RAM 103, the ROM 104 and the interface I / O device 105 as storage means having a divided memory space. Reference numeral 107 denotes a 4-input NOR (negative OR) circuit as detection means for detecting that a specific address has been designated, and the eighth, ninth, and tenth bits of the address are input. Also, 109 and 110 are OR gates as switch means for outputting a signal for inhibiting data writing to a specific address.
(OR) circuit, 111 is a chip select signal (select gate input) of the RAM 103, 112 is a chip select signal of the ROM 104, and 113 is a chip select signal of the I / O device 105. 114 is an on / off switch, 115 is a 16-bit address bus, 116 is an 8-bit data bus, 117 is a pulse output at regular intervals, 106 is a software runaway detection circuit, 118 is reset signal, 120 is write
A W / R (Write / Read) signal 121 is a final chip select signal of the RAM 103. In this embodiment, the address space of the RAM 103 is
A space of 2 kbytes from O (H) to OF7FF (H),
In addition, the area of the software volume used by the software is assumed to be an address of OFOO (H) to OFOFF (H). (Operation / Action) 1) First, at the manufacturing plant, the above-mentioned OFOOO
The case of setting the soft volume values at addresses (H) to OFOFF (H) will be described. FIG. 2 shows an operation sequence flowchart in this case. In this case, the changeover switch 114 is turned off (step S
21), one input of the NOR circuit 107 is set to “Hi” (High). As an example, a case where the contents of the address OFOOO (H) is rewritten will be described. The 8th, 9th, and 10th bits of the address input to the NOR circuit 107 are “Lo” (Low). Since there is a “Hi” input, the NOR circuit 107
Is "Lo" (step S22). A W / R pulse (negative logic) 120 is applied from the CPU 101 to the other input of the OR circuit 109, and the output of the OR circuit 109 becomes “Lo” (step S2).
3). Further, a signal (negative logic) for selecting the RAM 103 from the chip select signal 111 of the RAM 103 is applied to the other input of the OR circuit 110, and the output of the OR circuit 110 becomes "Lo" (step S24). , RA by chip select signal 121
M103 is selected (Step S25), OFOOO (H)
The contents of the address are rewritten (step S25). 2) Next, the case where the above factory adjustment is completed will be described with reference to the operation sequence flowchart of FIG. In this case, the switch 114 is turned on (step S21). As a result, one input of the NOR circuit 107 becomes “Lo”. Next, a case where the contents of the soft volume area OFOOO (H) are rewritten as in the above example 1) will be described. However, since the adjustment is completed at the manufacturing factory, the above-mentioned OFOO in the soft volume area
The operation of rewriting the contents of the address O (H) means that the software has run away. That is,
As already mentioned, this can occur within the time interval T in FIG. In this case, the other three inputs of the NOR circuit 107, ie, address 8,
Since the ninth and tenth bits are “Lo”, the output of the NOR circuit 107 becomes “Hi” (step S32), and
Since the output of the OR circuit 110 is fixed to “Hi” regardless of the two-input OR input of the OR circuits 109 and 110 (step S33), the RAM 103
Is not chip-selected by the signal 121 (step S3
4), no writing is performed. Thus, the write operation to the soft volume areas OFOOO (H) to OFOFF (H) is prevented (step
S35). As described above, turning on the change-over switch 114 causes the software to run out of control and invalidate the operation even if a write operation is performed in the soft volume area during the time interval T in FIG. be able to. In particular, when writing is necessary, it is possible to update the data of the soft volume by turning off the switch 114. Further, applications such as memory backup are also possible. FIG. 4 shows a timing chart of each signal in FIG. The normal RAM 103 rewrites data when a write signal (negative logic) 120 is applied from the CPU 101 while the chip is selected (“Lo” signal), but as shown in FIG. Even if "", the RAM 103 is not kep-selected, indicating that the data write signal 120 is ignored. (Other Embodiments) In the above embodiment, a case was described in which a write operation is prevented by 256 bytes from OFOOO (H). However, the present invention is not limited to this, and any soft volume value may be used. Needless to say, there is no problem. [Effects of the Invention] As described above, according to the present invention, the software volume value in the storage means used by the software of the control device may cause an erroneous write operation due to runaway of the software. Also, the contents of the storage means could not be changed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of a control circuit according to the present invention, FIG. 2 is an operation sequence flowchart for setting an initial soft volume value, and FIG. FIG. 4 is a timing chart of each signal in FIG. 1, and FIG.
FIG. 6 is a block diagram of an example of a conventional control circuit. FIG.
The figure is a timing chart of the pulse / reset signal at the time of software runaway in FIG. 101 CPU 102 Address decoder 103 RAM 106 Runaway detection circuit 107 NOR circuits (detection means) 109, 110 each OR circuit 114 Changeover switch (switching means) 120 Write signal 121 … RAM chip select signal

Claims (1)

(57) [Claims] A control circuit for writing data to a rewritable memory, comprising: an address bus for transferring address data designating an address for writing data to the memory; a data bus for transferring data to be written to the memory; Detecting means for detecting that the control circuit has specified a specific address of the memory via the address bus; andmanual operation can be performed independently of writing control by the control circuit, and the specific address is determined by the detecting means. Control means for outputting a signal for prohibiting the writing of data to the specific address via the data bus when the designation is detected. 2. The switch means enables the output of the detection means.
2. The control circuit according to claim 1, wherein output of a signal for prohibiting writing to the specific address is controlled by invalidating the signal.