JPH024936B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention has a main processor and a sub-processor, the main processor has a common memory, the sub-processor has a local memory, and a common memory. Regarding memory, it relates to a memory control method in a data processing system configured to be accessible from both a main processor and a sub-processor.

(b) Prior art and problems In recent years, microprocessors have become widespread, and data processing systems are often constructed by combining multiple microprocessors because of their low price and ease of use. It is.

Figure 1 shows an example of the configuration of such a data processing system. In the figure, 1 is a main processor consisting of a microprocessor, 2 is a sub-processor also consisting of a microprocessor, 3 is a common memory, and 4 is a local memory. , 5 is a read-only memory (ROM), 6 is a selection circuit, 7 is a DMA circuit,
8 and 9 are common buses. In Figure 1,
Although only one sub-processor is shown, there may be an example in which multiple sub-processors are provided depending on the system configuration.

In the figure, the local memory 4 is the sub-processor 2.
It is used only by the main processor 1 side, and is not used by the main processor 1 side. On the other hand, the common memory 3 is accessed via the DMA circuit 7 when the common memory 3 is used from the sub-processor side, which is used by both the main processor 1 side and the sub-processor 2 side. Also, although not shown,
It goes without saying that various I/O devices are connected to the common buses 8 and 9, respectively.

Here, the ROM 5 permanently stores a program for IPL (initial program loading), and when starting up the system on the sub-processor 2 side, the selection circuit 6 first selects the
ROM5 is selected and subprocessor 2 is
A startup operation is performed by accessing the ROM 5.

The reason why a ROM is used for IPL in this way is that microprocessors generally have a fixed startup address (for example, X'0000'), so it is appropriate to use a read-only memory.

However, when a ROM is used in this manner, it is not easy to change or modify programs after system configuration, resulting in a lack of flexibility.

(c) Purpose of the Invention The present invention solves the above problems, and on the subprocessor side, ROM is deleted and all read/write is performed.
The purpose is to measure the flexibility of system configuration by configuring it with writable memory.

(d) Structure of the Invention In order to achieve the above object, the present invention has a main processor and a common memory connected on a first common bus, a sub-processor and a local memory connected on a second common bus, In a data processing system configured such that the common memory can be accessed by both the main processor and the sub-processor, memory access by the sub-processor is in an access mode to the common memory or in an access mode to the local memory. memory selection means that holds access mode instruction information for instructing which memory is to be accessed and has an address information determination function and sends a memory selection signal to one of the memories to be accessed; The address conversion means is provided for converting into memory address information on the memory, and is sent from the processor when the memory access from the sub-processor is in the access mode to the common memory and the memory address information is within a predetermined range. The present invention is characterized in that the address information is converted by the address conversion means and sent to the common memory, and a selection signal is sent from the selection means to the common memory.

(E) Embodiment of the Invention FIG. 2 is a block diagram of a data processing device according to an embodiment of the present invention. In the figure, 10 is a main processor consisting of a microprocessor, and 11 is also a microprocessor. subprocessor, 1
2 is a common memory, 13 is a local memory, 14 is an address conversion circuit, 15 is a selection circuit, 16 is a 1-bit register, 17 and 18 are AND circuits, 1
9 and 20 are tri-state circuits, 21 is an address bus on the main processor side, 22 is a data bus on the main processor side, 23 is an address bus on the sub-processor side, 24 is a data bus on the sub-processor side, and 25 is a bus from the sub-processor 11. A read control line 26 is a write control line from the sub-processor 11, 27 is an activation signal line, 28 is a selection signal line to the local memory 13, and 29 is a selection signal line to the common memory 12.

In the figure, an address conversion circuit 14 converts the address on the address bus 23 based on address conversion control information set internally, and
This is a circuit that sends data onto the address bus 21. The selection conversion 15 also converts the sub-processor 11 based on the access mode instruction flag information set internally and the value of the input address information.
When memory access is made from the selection signal line 28
29 is turned on to select either the local memory 13 or the common memory 12.

Furthermore, the selection signal line 29 is connected to the AND circuits 17 and 18.
from the sub-processor 11 to the common memory 1.
When reading 2, the tri-state circuit 19 is turned on, and when writing from the sub-processor 11 to the common memory 12, the tri-state circuit 20 is turned on.

The operation of the embodiment will be explained below. When the main processor side performs a startup operation on the sub-processor side, the main processor 10 first sets common memory access mode information in an access mode instruction flag information holding register (not shown) in the selection circuit 15. In addition, the main processor 10
sets address translation control information in an address translation control information holding register (not shown) in the address translation circuit 14. Specifically, this address conversion control information is, for example, address information to be added to the address information sent from the address bus 23.

After setting the address conversion circuit 14 and selection circuit 15 in this way, the main processor 10 transfers the settings to the sub-processor 1 via the register 16.
Sends a start signal to 1. As a result, the sub-processor 11 starts reading from address X'0000'. The X'0000' address information on the address bus 23 is converted into an address in the address conversion circuit 14, and becomes address information for actually accessing the common memory 12.

Further, common memory access mode information is set in the selection circuit 15, and
Since the address X'0000' is within a predetermined address range, the selection signal line 29 is turned on for memory access from the sub-processor 11, and the common memory 12
is selected. Specifically, the selection signal line 29
The above signal can be considered the memory chip enable (CE) signal.

In this way, data read from common memory 12 is taken into subprocessor 11 via data bus 22, tristate circuit 19, and data bus 24.

FIG. 3 is a diagram showing the relationship between the address map on the main processor side and the address map on the subprocessor side. In the figure, 30 is the address map on the main processor side, 31 is the address map on the subprocessor side, and a is a common address map. The common memory address b in the memory startup mode is the local memory address in the common memory startup mode. The address conversion shown in FIG. 3 is performed by the address conversion circuit 14 shown in FIG. 2 as described above, and the address conversion shown in FIG.
Access is made to an address in the common memory 12 that is different from the address from 1.

Note that in common startup mode, accesses from subprocessor 2 to addresses X'0000' to X'7FFF' are performed to common memory 3 after address translation; Accesses from the sub-processor 2 to addresses X'8000' to X'FFFF' are made directly to the local memory 4.

Furthermore, in local memory startup mode, which is another mode, accesses from subprocessor 2 to addresses X'0000' to X'7FFF' are made to local memory 4, Address X′8000′ from ~
Access to address X'FFFF' is performed to the common memory 3 after address translation.

By configuring as above, conventionally,
The IPL information stored in the ROM can be stored in the common memory 3, and the subprocessor 2 can read this information from the common memory 3.

(F) Effects of the Invention According to the present invention, the ROM for IPL can be omitted, and the information for IPL can be read/written.
Since the information can be stored in a writable memory, it is possible to efficiently deal with changes in the system configuration.

Also, by having two access modes,
The sub-processor can operate independently regardless of the main processor's operation, allowing the entire system to operate efficiently.

[Brief explanation of drawings]

Figure 1 shows an example of the configuration of a conventional data processing system.
FIG. 2 is a block diagram of a data processing device according to an embodiment of the present invention, and FIG. 3 is a diagram showing the relationship of address maps in the common memory access mode. In FIG. 2, 10 is the main processor;
1 is a sub-processor, 12 is a common memory, 13 is a local memory, 14 is an address conversion circuit, 15
is a selection circuit.

Claims (1)

[Claims] 1. A main processor and a common memory are connected on a first common bus, a sub-processor and a local memory are connected on a second common bus, and the common memory is connected to the main processor and the local memory. In a data processing system configured to be accessible from both, retains access mode instruction information that instructs whether memory access by the subprocessor is in an access mode to the common memory or to the local memory. and a memory selection means that has an address information determination function and sends a memory selection signal to any memory to be accessed, and an address that converts the memory address information sent from the subprocessor into memory address information on the common memory. A conversion means is provided, and when the memory access from the sub-processor is in the access mode to the common memory and the memory address information is within a predetermined range, the address information sent from the sub-processor is converted by the address conversion means. A memory access control system characterized in that the selection signal is sent to the common memory from the selection means and the selection signal is sent to the common memory. 2. When the main processor starts the sub-processor, the main processor sends access mode instruction information to the memory selection means and causes the memory selection means to retain the information, and also sends address conversion control information to the address conversion means. ,
The main processor is configured to have address mode instruction information so that the information is held, and then a start signal is sent from the main processor to the sub-processor to cause the sub-processor to access the common memory or the local memory. A memory access control method according to claim 1, characterized in that: