JPS62226345A - Lsi for input output memory access - Google Patents

Lsi for input output memory access

Info

Publication number
JPS62226345A
JPS62226345A JP6990486A JP6990486A JPS62226345A JP S62226345 A JPS62226345 A JP S62226345A JP 6990486 A JP6990486 A JP 6990486A JP 6990486 A JP6990486 A JP 6990486A JP S62226345 A JPS62226345 A JP S62226345A
Authority
JP
Japan
Prior art keywords
read
write
memory
input
counters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6990486A
Other languages
Japanese (ja)
Inventor
Yuji Watabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6990486A priority Critical patent/JPS62226345A/en
Publication of JPS62226345A publication Critical patent/JPS62226345A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable highly efficient accessing when accessing an input-output memory sequentially by using an LSI for memory access and thereby simplifying circuit configuration.
CONSTITUTION: Initial value of count is set to counters (UCNTR/MCNTR/ LCNTR) 1W3 by data inputted from outside. Increment or decrement from the initial value of count is started by clocks (CKU.CKM.CKL) and count up/down signals (UP/DOWN) given from outside and the value is outputted. Memory address for higher rank and memory address for lower rank correspond respectively to counters 1W3. When READ/WRITE is made to input-output ports allotted beforehand to counters 1W3, a decoder 4 decodes addresses and outputs specified signals to a specified counter block. When READ/WRITE of data is made to the input-output port itself, a READ/WRITE of data is made to the input-output port itself, a READ/WRITE signal for a memory is outputted, and READ/WRITE is performed actually to the memory.
COPYRIGHT: (C)1987,JPO&Japio
JP6990486A 1986-03-28 1986-03-28 Lsi for input output memory access Pending JPS62226345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6990486A JPS62226345A (en) 1986-03-28 1986-03-28 Lsi for input output memory access

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6990486A JPS62226345A (en) 1986-03-28 1986-03-28 Lsi for input output memory access

Publications (1)

Publication Number Publication Date
JPS62226345A true JPS62226345A (en) 1987-10-05

Family

ID=13416149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6990486A Pending JPS62226345A (en) 1986-03-28 1986-03-28 Lsi for input output memory access

Country Status (1)

Country Link
JP (1) JPS62226345A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0764854A (en) * 1993-08-11 1995-03-10 Koninkl Ptt Nederland Nv Arrangement apparatus for connection of processor to memory as well as system provided with processor and with arrangement apparatus for connection of memory to processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0764854A (en) * 1993-08-11 1995-03-10 Koninkl Ptt Nederland Nv Arrangement apparatus for connection of processor to memory as well as system provided with processor and with arrangement apparatus for connection of memory to processor

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