JPS62226345A - Lsi for input output memory access - Google Patents

Abstract

PURPOSE:To enable highly efficient accessing when accessing an input-output memory sequentially by using an LSI for memory access and thereby simplifying circuit configuration. CONSTITUTION:Initial value of count is set to counters (UCNTR/MCNTR/ LCNTR) 1-3 by data inputted from outside. Increment or decrement from the initial value of count is started by clocks (CKU.CKM.CKL) and count up/down signals (UP/DOWN) given from outside and the value is outputted. Memory address for higher rank and memory address for lower rank correspond respectively to counters 1-3. When READ/WRITE is made to input-output ports allotted beforehand to counters 1-3, a decoder 4 decodes addresses and outputs specified signals to a specified counter block. When READ/WRITE of data is made to the input-output port itself, a READ/WRITE of data is made to the input-output port itself, a READ/WRITE signal for a memory is outputted, and READ/WRITE is performed actually to the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an LSI for input/output memory access suitable for use in a microcomputer system.

(Prior art) In microcomputer systems that require real memory (extended memory) that is larger than the memory space that can be directly accessed by the CPU, a part of the memory is mapped to the input/output space and a memory address is written to the input/output port. The method of access is usually used.

(Problems to be Solved by the Invention) However, in the nine conventional methods described above, an address is specified and stored as data in the friend output port.
3 times of input/output■ ITE 9 operations are required, which has the disadvantage of slowing down memory access execution time.On the other hand, as a way to somewhat improve this problem, a counter circuit is provided at the memory address generation input/output port, and a certain address When accessing memory consecutively, it is also possible to specify the first address and then access the following addresses by incrementing the counter.

However, in this case, since a counter IC is required, it is difficult to integrate the board.

The present invention has been made in view of this, and an object of the present invention is to provide an LSI for memory access that does not affect the memory access time and achieves full integration of the board.

[Structure of the Invention] (Ninth Means for Solving the Problems) The present invention achieves the above-mentioned nine objects by providing a memory access LSI with an initial value set according to a clock n1 given from the outside. There are several counters that perform quick counting up and down, input/output port addresses given from the outside, and input/output that decodes the READ7■ITE signal and assigns count clocks to selected companions of the above counters in advance. Note 1 for port
．． It consists of a decoder that supplies the I READ and I TE signals.

[Operation] With the configuration described above, first, the input/output V/RITB signal and input/output port address given from the outside are decoded by the decoder, and the data on the data bus is loaded into the counter to set the initial value. . Furthermore, by decoding the input/output ■ITE signal given from the outside and the input/output port address, the memory WRITE signal is made active, and according to the address output by the color/receiver, data is read and output at a predetermined address in the external memory. /WRIT
E I will do it. Also, at this time, a count clock is output from the decoder, and the address is updated in the designated direction by the nine count up/down signals set in advance in the counter.

(Example) Hereinafter, examples of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1 to 3 are counters (UCNTR/MCN
TR/LCNTR), and the initial value of the count is set by externally input data. Also, it starts incrementing or decrementing from the above-mentioned t count initial value using a clock (CKU''CKM-CKL) and a count up/down signal (UP/DOWN) applied from the outside, and outputs that value. Counters 1 and 1 for middle and low rank respectively.
Corresponds to 2.3.

4 is a decoder. Decoder 4 sends REAI to input/output ports assigned in advance to counters 1 to 3.
)/WRITE, the address is decoded and a predetermined signal such as a clock signal is output to a predetermined counter block in the figure. Also, to the input/output port itself y' - t
READ/vRITE j le (!: Memo! J (D READ/WRI TE signal is output, and READ/WRI TE to the memory is performed with a smile. In addition, 5
is a data bus, and 6 is an address bus.

The operation will be explained in detail below.

First, the upper memory address is written as data to the input/output port (counter 1). Specifically, input/output■IT
E signal (IOW'r) and input/output port address (l0
ADR)- is decoded by the decoder 4, and among the data load signals (LDU-LDM-LDL), the upper one (
When LDU) is activated, the data on the data bus 5 is loaded into the counter 1, and this 1st shift is set as the initial count value. At the same time, this value is output onto the address bus 6 as an upper memory address. Similarly,
The middle address and the lower address are set in counters 2 and 3, and the memory address setting is completed.

Next, READ/WRITE of memory data is performed via the port. When data is sent to the port, the input/output WRITE signal (10WT), input/output port address address δADR'ii decoding) and memory write signal (WRITE)'i are activated.

This allows WRITE data to be stored in an external memory (not shown).
Data on the data bus 5 can be written to a predetermined address from the signal and address (address bus 6).

The same applies to READ.

In addition, at the time of RIi:AD/WRITE to the input/output port, the count clock signal (CKU - CKM - CKL
) is output, and counters 1 to 3 count up or down in the direction specified by the preset count up/down signal (UP/DOWN). Therefore, once reading/writing to the memory is completed, the next address is automatically set as the memory address and the memory is in a friend state. Here, if you want to access all memory continuously from the first accessed memory address,
Using this address automatic count up/down function, m7 ITE operations to the memory can be performed centrally by simply performing data READ/WRITE to the input/output port.

Note that 'rct' and 're2 are terminal count signals, which inform that the count 1 shift has reached the maximum or minimum as a result of count up/down. This signal is input as an enable signal to the next higher counter (2 and 1, respectively), and the counter synchronizes with the clock and performs counting only at 9 o'clock. As a result, counters 1 to 3 operate as one counter as a whole. CLR is a counter and decoder initialization signal.

[Effects of the Invention] As explained above, by using the memory access LSI according to the present invention in a system requiring an input/output memory, the circuit configuration can be simplified and the board can be integrated.

Furthermore, according to the present invention, particularly efficient access to Fi is possible when sequentially accessing the input/output menus.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1.2.3... Counter, 4... Decoder, 5...
・Data bus, 6...address bus.

Claims (1)

[Claims] Some counters have initial values set and count up/down according to externally applied clocks, as well as externally applied input/output port addresses and R.
a decoder that decodes the EAD/WRITE signal and outputs a count clock to the selected one of the counters and a memory READ/WRITE signal to the selected one of the input/output ports allocated in advance; Memory RE output by this decoder
READ/W of the externally connected memory based on the AD/WRITE signal and the address output by the above counter.
An input/output memory access LSI characterized by performing RITE.