JP2000276399A - Address control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate control regarding addresses by controlling the addresses when a memory of another system is controlled according to identification information set by a setting means and addresses regarding a common path area prescribed by an address prescribing means. SOLUTION: A 1st CPU 1 is able to perform write/read control over a 1st memory 3 by a 1st memory control part 2. The 1st CPU 1 is able to control a 2nd memory 9 and the internal registers of a 2nd memory control part 8, but when the 2nd memory 9 is controlled, settings regarding the control over the 2nd memory 9 are made in the internal registers of the 1st memory control part 2. According to the settings, the 1st memory control part 2 generates the addresses of the area of the 2nd memory 9 and informs the 2nd memory control part 8 through a common bus 6 that the 1st CPU 1 is to control the 2nd memory 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address control system in a system including a plurality of CPUs, which can easily control an address when controlling a memory under the control of a CPU of another system.

[0002]

2. Description of the Related Art Conventionally, when a memory shared by a plurality of CPUs is controlled, as shown in FIGS. 6 and 7, an address to which a region to be controlled is mapped is used as it is.

[0003]

Since the conventional address control system for controlling a memory under the control of a CPU of another system has the above-described configuration, the value to be set becomes complicated, and the internal register is not stored. The structure was also complicated.

The present invention has been made to solve the above-described problem, and provides an address control method capable of easily controlling an address when controlling a memory under the control of a CPU of another system. The purpose is to do.

[0005]

According to the address control method of the present invention, there is provided a CPU which controls the control of a self system, a system bus, and a CPU which can be written and read by the CPU via a memory bus. And a memory control unit that controls the memory via the memory bus.This is an address control method for sharing the memory of another system between the respective systems. The common bus connecting between the memory control units, the address defining means for defining the addresses of the internal register area of the own system, the memory area of the own system, the common bus area, and the identification information about the control of the memory of the other system are included. Setting means to be set; the identification information set by the setting means; and the address defining means. Ri on the basis of the address of the defined the common bus regions, characterized in that a control means for controlling the address at the time of controlling the memory of another system.

An address control method according to the present invention is for identifying whether control of a memory of another system is control of a memory area of the other system or control of an internal register area in a memory control unit of the other system. And generating an address for controlling the memory of the other system based on the identification information of the common bus and the address of the common bus area of the common bus connecting the own system and the memory control unit of the other system. The memory of the other system is controlled by the generated address via the memory control unit of the system, and the address generation when the memory under the control of the CPU of the other system is controlled by the own system is facilitated.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below. In the address control method according to an embodiment of the present invention, when controlling a shared memory, each CPU operates an internal register of its own memory control unit without directly using an address mapped for an area to be controlled. It is characterized in that the memory area and the internal register area can be easily controlled only by setting.

FIG. 1 is a block diagram showing a configuration of an address control system according to an embodiment of the present invention. As shown in FIG. 1, this address control system is composed of, for example, two systems, and a first system includes a first CPU (address defining means, control means) for controlling the control of the first system. 1) First memory 3 capable of controlling writing and reading by first CPU 1 via first system bus 4 and first memory bus 5, and first memory 3 via first memory bus 5 To control the memory 3 of the first
(A memory control unit of the own system) 2.

[0009] Similarly to the first system, the second system has a second C which controls the control of the second system.
PU 7, second memory (memory of another system) 9, second memory bus 11 capable of controlling writing and reading by second CPU 7 via second system bus 10 and second memory bus 11 And a second memory control unit (memory control unit of another system) 8 that controls the second memory 9 via the CPU.

The first CPU 1 can control writing and reading to and from the second memory 9 via the common bus 6, and similarly, the second CPU 7 can control the first memory 1 via the common bus 6. The writing and reading of the memory 3 can be controlled.

The first CPU 1 can control writing and reading to and from the first memory 3 via the first system bus 4, and the second CPU 7 can control the second system bus 10. The writing and reading of the second memory 9 can be controlled via the.

FIG. 2 is a block diagram showing the internal structure of the first memory control unit 2. The first internal register unit 12 for setting control conditions of the first memory control unit 2, the common bus 6, and the The first address generator 13 generates an address signal for one memory bus 5.

The first address generator 13 includes a first memory address generator 14 for generating an address signal for the first memory 3 and a first common bus for generating an address signal for the common bus 6. It comprises an address generation unit (control means) 15.

FIG. 3 is a block diagram including the internal structure of the first internal register section 12. The first internal register section 12 includes a plurality of internal registers (setting means) 16, 1
7, 18,... 19, 20.

The configuration of the first system is the same as that of the second system.

When the first CPU 1 controls the second memory 9, the control of the second memory 9 is set in the first internal register section 12 of the first memory control section 2. When the control of the second memory 9 is set in the first internal register section 12, the first address generation section 13
As a result, the first common bus address generator 15 outputs an address signal for the second memory 9 to the common bus 6.

The second memory control unit 8 recognizes that the first CPU 1 controls the second memory 9 based on the address signal output to the common bus 6, and the second memory 9 To output an address signal. As a result, the first CPU 1 is configured to be able to control the second memory control unit 8.

When the first CPU 1 controls writing and reading to and from the first memory 3, a signal indicating that an access target is an area of the first memory 3 is sent to the first system bus. 4 is output. Then, the first memory address control unit 14 of the first address generation unit 13
Is configured to be able to control by outputting an address signal for the first memory 3 to the first memory bus 5.

Next, the operation will be described. First CP
U1 can control writing and reading of the first memory 3 by the first memory control unit 2, and can also control the second memory 8 under the control of the second CPU 7.
Writing and reading can be controlled via the common bus 6. The first CPU 1 has a second memory 9 and a second memory 9.
Can be controlled with respect to the internal register of the memory control unit 8, but when controlling the second memory 9, the control of the second memory 9 is set in the internal register of the first memory control unit 2. . Based on this setting, the first memory control unit 2 generates an address which is an area of the second memory 9, and the first CPU 1 sends the address to the second memory control unit 8 via the common bus 6. A notification that the user wants to control the second memory 9 is given.

As described above, when controlling the second memory 9, the first CPU 1 can easily perform the control without using the address of the second memory 9.

Next, the operation of the present embodiment will be further described with reference to FIG. 4, FIG. 5, FIG. 6, and FIG. FIG.
Is an address map of the first internal register unit 12, the first memory 3, and the common bus 6, and the register in the second memory control unit 8 and the second memory 9 are similarly address-mapped.

FIG. 5 shows one internal register of the first internal register section 12. If the internal register 16 is the internal register shown in FIG.
6, the first internal register area is (1) as shown in FIG.
000 0000H)
The address is (1000 0000H).

As shown in FIG. 5, the internal register 16 is defined by 32 bits from bit 0 to bit 31 since the first CPU 1 has a 32-bit data bus. In this internal register 16, only one bit of bit0 is valid. For example, when "0" is set to this bit, the first CPU 1 controls the second memory 9, and "1" is set. Then, it indicates that the control is for the internal register in the second memory control unit 8.

When the first CPU 1 controls the addresses (2000 0000H) of the second memory 9, first, “1” is set to bit 0 of the internal register 16 shown in FIG. set.

Since the area of the common bus 6 is mapped to (3000 0000H) units as shown in FIG. 4, the first CPU 1 is assigned to (2000 0000H) units of the second memory 9 of the second system. When writing data to the internal register 16 after setting the internal register 16 shown in FIG.
(3000 0000H) is written to the unit.

The address controlled by the first CPU 1 is (3
000 0000H), the first memory 3 does not control the first memory 3. Therefore, the first memory address controller 14 in the first address generator 13 outputs an address to the first memory 3. do not do.

The first common bus address control unit 15
Since the set value of bit 0 of the internal register 16 shown in FIG. 5 is “1” and the address controlled by the first CPU 1 is (3000 0000H), the first CPU 1 Recognizing that it is control,
An address (2000 0000H), which is an area of the second memory 9, is output to the common bus 6.

In this case, the configuration of the address mapping of each system shown in FIG. 4 (internal register area, memory area)
Are the same, the first CPU 1 outputs the address (2000 0000H) units, which are areas of the second memory 9, as they are. If they are different, it is necessary to know the address mapping configuration of the partner system in advance. As a result, the second memory control unit 8 outputs the address to the second memory 9 so that the first C
The control of the second memory 9 by the PU 1 becomes possible.

As described above, according to the present embodiment, when the internal register area is originally controlled, the internal register area is mapped to (1000 0000H) units, and as shown in FIG. Is set using 32 bits, and the same applies to the case of the memory area as shown in FIG. 7, but it is determined whether the register area or the memory area by one bit of bit 0 of the internal register shown in FIG. With this configuration, the internal structure of the register is simplified, and since only one bit is set, control is facilitated, and there is an effect that an address control system with improved reliability can be provided.

Next, another embodiment of the present invention will be described. The address control method according to the present embodiment has the same basic configuration as that of the above-described embodiment, but further includes a CPU.
In this embodiment, the internal register uses only one bit as shown in FIG. 5 while the unused bit is used to control the memory under which CPU. Is defined as a bit that can be identified, thereby facilitating the determination of the memory to be controlled.

As an example, the internal register b shown in FIG.
For it1 and bit2, the setting under “00B (binary)” is the memory under the control of CPU1, the setting under “01B” is the memory under the control of CPU2, and the setting under “10B” is the control under the control of CPU3. In the case of setting the memory, "11B", even when the number of CPUs increases, such as the memory under the control of the CPU 4, the selection can be easily made.

[0032]

As described above, according to the present invention, whether the control of the memory of the other system set by the setting means is the control of the memory area of the other system, Based on the identification information for identifying whether the control is the control of the internal register area, and the address of the common bus area of the common bus connecting between the own system and the memory control unit of the other system defined by the address defining means. And the control means for controlling the address when controlling the memory of the other system, so that the configuration of the identification information is simplified by coding the lower order bits according to the number of other systems. As a result, the configuration of the register becomes easy, and since only one bit is set, the control becomes easy, and the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an address control system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal structure of a first memory control unit in an address control system according to an embodiment of the present invention.

FIG. 3 is a block diagram including an internal structure of a first internal register unit in an address control system according to an embodiment of the present invention;

FIG. 4 is an address map of a first internal register unit, a first memory, and a common bus in an address control system according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram showing one internal register in a first internal register unit in an address control system according to an embodiment of the present invention;

FIG. 6 is an explanatory diagram of a conventional address control method showing an address of a register set in the (1000 000H) range when controlling a memory shared by a plurality of CPUs.

FIG. 7 is an explanatory diagram of a conventional address control method showing addresses of a memory area set in the (200000H) range when controlling a memory shared by a plurality of CPUs.

[Explanation of symbols]

1. First CPU (address defining means, control means),
2... 1st memory control unit (memory control unit of own system), 3... 1st memory, 4... 1st system bus, 5... 1st memory bus, 6. …
... second memory control unit (memory control unit of another system)
9: second memory (memory of another system), 15:
A first common bus address generator (control means), 16...
... Internal register (setting means).

Claims (4)

[Claims] 1. A CPU for controlling the control of a self system,
A system bus, a memory under the CPU that can be written and read by the CPU via a memory bus, and a memory control unit that controls the memory via the memory bus. An address control method for sharing the memory of another system, which includes a common bus connecting between the own system and each memory control unit of the other system, an internal register area of the own system, a memory area of the own system, the common bus area, and the like. Address defining means for defining the address of the memory; setting means for setting identification information for controlling the memory of the other system; the identification information set by the setting means; An address for controlling the memory of another system based on the address of the common bus area An address control method, comprising: control means for controlling a dress. 2. The apparatus according to claim 1, wherein the setting unit sets identification information for identifying whether the control is for controlling a memory area of the other system or for controlling an internal register area in a memory control unit. Item 2. The address control method according to Item 1. 3. The method according to claim 1, wherein the setting means determines whether to control the memory area of the other system or to control the internal register area in the memory control unit. 3. The address control method according to claim 2, wherein: 4. The controller according to claim 1, further comprising: a controller configured to determine an address of a memory area or an internal register area of another system based on the identification information set by the setting unit and an address of the common bus area specified by the address specifying unit. 4. The address control method according to claim 1, wherein the address is generated, the generated address is output to a common bus, and a memory of the other system is controlled via a memory control unit of the other system.