JPH0713915A - Bus control system - Google Patents

Abstract

PURPOSE:To allow an activated 10 module to identify the I0 module which activates it by embedding the IO module number of the origin of activation into one part of an address to be outputted to a system bus. CONSTITUTION:In a multi-processor system in which at least more than two IO modules 1 and 2 are connected through a system bus 3, the IO modules 1 and 2 to which their original module numbers are allocated are equipped with means 4 and 5 which fixedly output their own module numbers. Then, when the arbitrary module 1 performs an access through the system bus 3 to the other IO module 2, the IO module number of the origin of activation is embedded from the fixed outputting means 4 to one part of an address 6 to be outputted to the system bus 3. Therefore, in the IO module of the origin of activation, the IO module number is set regardless of a software in the IO module, and even when the IO module number is different, the software in the IO module is made equal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system for allocating an address to a bus of a computer system, and in particular, in a multiprocessor system, data can be easily exchanged when an IO module is intelligent. It relates to a possible bus control system.

[0002]

2. Description of the Related Art Conventionally, a plurality of processors and IOs have been used.
A multiprocessor system is used in which the modules are connected to a common bus. And usually, the address map of the bus in the computer system is
It is uniquely defined by the IO module to be activated (extended I / O board development standard (April 1991, refer to AX Council). In conventional systems, the IO address is activated. It was only assigned individually to the IO modules, and the information was not included in the IO module that activated it, that is, in a normal processor system, one processor and a plurality of IO modules were used. -Is connected to the bus and must be
Since the module was being activated, it was not necessary to identify the opponent who activated it. However, in a multiprocessor, multiple processors and multiple IO modules are combined into one.
Since it is connected to the bus of the book, when a certain IO module is activated, the IO module side cannot know from which processor the activation is applied. When the IO module is intelligent, only a plurality of IO modules are connected to one bus, or a plurality of processors and a plurality of IO modules are connected to one bus. In some cases, an IO module activates another IO module. Therefore,
The activated IO module cannot determine which IO module is the activated IO module from the activated address.

[0003]

As described above, if one processor is regarded as one IO module in a multiprocessor via the system bus, the IO module to be activated includes a plurality of IO modules. -There is a possibility that the IO module will be activated, and the activated IO module may have to notify the activated IO module of the processing result and the like. Therefore, the activated IO module needs to know from which IO module the activation is started. Also, if the IO module is intelligent and configured to execute the software, for both existing processor and IO module (eg disk device) software,
We would like to avoid making changes for multiprocessors in terms of both labor and cost. An object of the present invention is to solve the conventional problems described above and to provide a bus control system in which an activated IO module can identify the activated IO module.

[0004]

In order to achieve the above object, in the bus control system of the present invention, at least two IO modules (1, 2) are connected via a system bus (3). In a multiprocessor system, each IO module (1, 2) to which a unique module number is assigned is provided with means (4, 5) for fixedly outputting its own module number. When the IO module (1) of another accesses the other IO module (2) through the system bus (3), the system bus (3)
The IO module number of the activation source from the fixed output means (4) is embedded in a part of the address (6) to be output to.

[0005]

According to the present invention, when one IO module of a multiprocessor system is activated from a plurality of IO modules, the activated IO module is the activated IO module. It is stored by identifying it from the module number part of the address of the system bus.
The activated IO module performs a series of processes for this activation, and then activates the IO processing result.
In the case of notifying the module, the IO module number of the starting source stored in advance is used and it is sent as the other party. As the IO module number, a unique number is set for each IO module. This setting value is the mounting position in each IO module or hardware work order or I
It is set by the ROM in the O module. The IO module automatically sends out this module number as a part of the address to be output to the system bus when activating another IO module. The activated IO module decodes the address portion (that is, the destination address) other than the module number, and identifies whether or not the IO module is activated. The activated IO module can read the number of the activated IO module from the address of the system bus as needed. in this way,
The IO module that is the boot source uses the IO module number IO
Since the setting is made independently of the software in the module, the software in the IO module can be the same even if the IO module numbers are different.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a multiprocessor system showing an embodiment of the present invention. In FIG. 1, 1, 2
Are IO modules, 3 are system buses, and 4, 5
Is an order number for a module number, 6 and 8 are output address registers, 7 and 9 are input address registers, 10 and 11 are address comparators, and 12 and 13 are MPU (microprocessor unit). Although there are a plurality of IO modules connected to the system bus 3, only two IO modules 1 and 2 are shown here. Each of the IO modules 1 and 2 outputs the values of the output address registers 6 and 8 to the system bus 3. After that, each of the IO modules 1 and 2 latches the address from the system bus 3 in the input address registers 7 and 9. The work modules 4 and 5 have their own IO module numbers (1) and (2), respectively.
Is fixedly applied, the address comparators 10 and 11 compare the bits 15 to 8 of the address input from the system bus 3 with the addresses of the notes (1) and (2). If they match, it is determined that the command is addressed to itself, and bits 7 to 7 of the input address registers 7 and 9
Read the 0 function section. On the other hand, at the time of output, the work numbers (1) and (2) of the module number are input to bits 12 to 8 of the output address registers 6 and 8, respectively, and become the IO module number portion of the address output source. . M
The addresses output from the PUs 12 and 13 are input to bits 15 to 12 and bits 7 to 0 of the output address registers 6 and 8, and serve as a device number part and a function number part.

FIG. 2 is a format diagram showing the system bus address allocation in FIG. In FIG. 2, of the 16-bit address, bits 15 to 12 are device number parts (DVN) (15), that is, destination addresses, and bits 11 to 8 are module number parts (MD).
N) (16), which is the output source address, bit 7
˜0 is a function number part (FUN) (17), that is, a command part or a register designating part. Besides this,
The data portion of bits 15 to 0 is continuously output. The start address and the like in the memory are stored in the data section. As described above, the device number section 15 is for designating an IO module, and in this system, a maximum of 16 modules can be designated by 4 bits. Module number part 16
Specifies the IO module number of the address output source. Further, the function number section 17 is
It designates a register or command in the P module. The IO module that activates the system bus 3 takes in the set module number (16) and outputs it to the system bus 3 as a part of the address. The activated IO module decodes (15) other than the module number part (16) of the system bus 3 and judges whether the activation is for its own IO module. . The IO module takes in the module number part (16) of the start-up address for itself. The IO module, after performing processing for activation, notifies the IO module of the activation source of the processing result. The address of this notification destination uses the module number (16) obtained at the time of activation.

FIG. 3 is an operation flow chart of an IO module showing an embodiment of the present invention. Here, MP is changed from the MPU 12 in the IO module 1 to the IO module 2.
By activating self-diagnosis of U13, MPU2
Shows the case where the self-diagnosis is performed and the result is notified to the IO module 1. First, the MPU 12 outputs the device number (HEX2) of the IO module 2 to bits 15 to 12 of the address, and the function number (HEX00) of command reception to bits 7 to 0 of the address, and outputs the data.
(HEXFFFF) indicating the start of self-diagnosis is output as the data (step 101). Next, in the output address register 6 of the IO module 1, the address from the MPU 12 and the value (HEX2) of the work note (1) of the module number of the IO module 1 are mapped to the address bits 11 to 8. -Step 102. Next, the IO module 1 receives this address (HEX21FF) and data (HEXFFF).
F) is output to the system bus 3 (step 103).
Next, the IO module 2 latches the address (HEX21FF) of the system bus 3 in the input address register 9 (step 104). Next, IO module 2
Bits 15 to 12 of the address (HEX21FF)
And the value of Engineering Note (2), which is your module number (HE
X2) is compared with the address comparator 11, and when the results match, it is possible to identify that the access is to the IO module 2 of its own, so the data (HE
XFFFF) is fetched (step 105).

Next, the MPU 13 of the IO module 2
IO from the value of bits 11 to 8 of the input address register 9
Knowing that the startup is from module 1, bit 7 ~
A value of 0 (HEX00) is analyzed and it is determined that the command is a command. Further, by analyzing the data (HEXFFFF), it is known that the command is a self-diagnosis command (step 106). Next, MPU of IO module 2
After performing self-diagnosis, the result of address 13
Write to bits and 16 bits of data. That is, the device number of the IO module 1 is set in the address bits 15 to 12, the resulting function number (HEX01) is set in the address bits 7 to 0, and the data (HEX0000) if the self-diagnosis is normal. If it is not normal, the data (HEX0001) is written (step 107). Next, in the output address register 8 of the IO module 2,
Margin the module number work note (2) to the address bits 11 to 8 (step 108), and add the address (HE
X1201) is output to the system bus 3 (step 109).

On the other hand, the IO module 1 fetches the value of the address bits 15 to 12 (HEX1) by fetching the address of the system bus 3 into the input address register 7, and outputs the module number of the module number by the address comparator 10. Compare with the value in Note (1) (HEX1). Since the comparison results match, it is known that the IO module 1 is activated (step 110). Next, M of IO module 1
PU12 is the value of address bits 11-8 (HEX2)
From this, it is known that the activation is performed by the IO module 2, and it is discriminated from the value (HEX01) of the address bits 7 to 0 that the result is the self-diagnosis. The value of the data (H
From EX0000), it is known that it was normal (step 111). FIG. 4 is an explanatory diagram of a method of using the space of the system bus showing another embodiment of the present invention. 1 to 3, the present invention is applied to all the spaces of the system bus 3, but the present invention is not applied to all the spaces of the system bus 3 as shown in FIG. It is also possible to select use or non-use of the present invention. That is, in FIG. 4, the IO modules 1, 3, 5, ...
.., 16 show the case where the present method is not used but the one by the normal addressing is used. I
The O modules 1, 3, 5, ... 15 are often activated from other IO modules, and the IO modules 2, 3.
When the other IO modules are activated in many cases, 4, 6, ... 16 are preferably assigned as described above.

FIG. 5 is a bus configuration diagram of a multiprocessor system showing still another embodiment of the present invention. Figure 1
In the embodiment shown in FIG. 3, the system bus 3 is composed of the address bus and the data bus as in the prior art. That is, as the boot source IO module number,
The method was to enter the module number from the work inside the module and make it a fixed part of the address. On the other hand, FIG. 5 shows a method of separating the boot source IO module number bus from the others. That is, as the system bus 3, a boot source IO module number bus 20 is provided in addition to the data bus 18 and the address bus 19. Therefore, when the address and data are output from the activation source, the received module can know the IO module number of the activation source by capturing the IO module number bus 20 and detecting the number. it can. In this way, by using the boot source module number included in the address, the IO module is
Good exchange of data and commands between the rules. Moreover, even when the MPU is not built in the IO module, the control can be performed in the same manner.

[0012]

As described above, according to the present invention,
When an IO module, which is a multiprocessor system, starts another IO module, the started IO module can immediately know the starting IO module. It is possible to give and receive smoothly. Also, since the boot source IO module outputs the module number by the hardware note, the software in the IO module does not care about its own module number The module can be activated. As a result, in a multiprocessor in which an MPU is built in an IO module and coupled via a system bus, each processor can be operated by the same software. Further, since the design can be done without considering the module number of oneself and a plurality of MPUs can be operated by the same software, the man-hours for designing the software can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multiprocessor system showing an embodiment of the present invention.

FIG. 2 is a diagram showing address allocation of a system bus in FIG.

FIG. 3 is an operation flow chart of an IO module showing an embodiment of the present invention.

FIG. 4 is a diagram showing a method of using space in a system bus according to another embodiment of the present invention.

FIG. 5 is a diagram showing a method of separating a boot source IO module number bus according to still another embodiment of the present invention.

[Explanation of symbols]

 1, 2 IO module 3 System bus 4, 5 Modular number processing note 6, 8 Output address register 7, 9 Input address register 10, 11 Address comparator 12, 13 MPU 14 System bus address allocation 15 Devices Number part 16 Module number part 17 Function number part 18 Data bus 19 Address bus 20 Starting source IO module number bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuya Sakano 3-10-22 Sakae, Naka-ku, Nagoya-shi, Aichi Hitate Chubu Software Co., Ltd.

Claims (1)

[Claims] 1. In a multiprocessor system in which at least two or more IO modules are connected via a system bus, each IO module assigned a unique module number has its own module. A means for fixedly outputting the module number is provided, and when any IO module accesses another IO module via the system bus, a part of the address to be output to the system bus,
A bus control system characterized by embedding an IO module number of an activation source from the fixed output means.