JPH04326140A - Memory controller - Google Patents

Abstract

PURPOSE:To change the kind of a memory to be used according to the purpose by providing a timing generating means which outputs a control signal corresponding to a storage element connected according to information held in a storage kind holding means. CONSTITUTION:When the DRAM fitted to the memory element 5a is replaced with an SRAM, a maximum address and a minimum address are inputted on a keyboard 3 so as to assign the memory matching the storage capacity of the SRAM. The input data are held in registers in an address specification device 11a from a data bus through a CPU 1. Further, a memory type is inputted on the keyboard 3 and its data is held in the high-order two-bit registers of a memory type register 14 from the data bus through the CPU 1. The values of the above registers are only changed and then a signal for the SRAM is outputted by a timing generation device 15 when the memory element 5a is accessed, thereby controlling the memory element 5a.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device used in, for example, a personal computer.

0002

2. Description of the Related Art In recent years, static RAM (hereinafter referred to as SRA) is one of the semiconductor memory devices used as storage means.
There are memory types such as dynamic RAM (hereinafter referred to as DRAM), pseudo-static RAM (hereinafter referred to as PSRAM), and read-only memory (ROM), each of which has a different memory control signal. Therefore, a memory control device is required depending on the memory type, and each time a new product is developed, the memory control device has to be redesigned for the type of memory to be installed. Furthermore, in order to expand the memory area, the user is limited to being able to connect only predetermined memory types.

0003

[Problems to be Solved by the Invention] Conventional memory control devices for personal computers have different control signals depending on the memory type, so the type of memory installed in the personal computer is uniquely determined at the design stage. . Therefore, the memory control device lacks redundancy and expandability, and has had to be redesigned every time a new personal computer is developed. In addition, the user can only expand the memory area by using the memory type determined for the personal computer, which has poor expandability. The present invention has been made in view of the above points, and an object of the present invention is to provide a memory control device that can be controlled regardless of the type of memory used. [Structure of the invention]

0004

[Means for Solving the Problems] In the first aspect of the present invention, storage elements for storing data are classified into types depending on the signals controlled, and the storage elements used in the storage means are classified into types depending on the signals controlled. a memory type holding means for holding information representing a type; and a timing for receiving the information held by the memory type holding means and outputting a control signal corresponding to the type of the storage element when the memory element is accessed; It is equipped with a generating means.

[0005] Furthermore, in the memory control device of the first claimed invention, when a memory element that requires refreshing is used as the memory element, the second claimed invention selects the memory element that requires refreshing and performs refreshing. The refresh control means is provided with a refresh control means for outputting a signal.

[0006]

[Operation] In the first invention of the present application, the storage element holds data, and depending on the difference in the controlled signals, the dRAM
, SRAM, PSRAM, etc. The storage type holding means holds information representing the type of memory element used in the storage means. The memory type holding means is a CPU.
When the storage element is accessed from the storage device, etc., information representing the type of the storage element held therein is sent to the timing generation means. The timing generating means sends a control signal for the storage means being used to the storage means based on the received information.

[0007] This makes it possible to change the type of memory used depending on the intended use, and it becomes unnecessary to develop a new memory control device every time a personal computer is developed. Furthermore, the user can change the type of memory as needed.

Furthermore, a second invention of the present application is the memory control device of the first invention of the present application, in which the memory element includes a memory element that requires a signal for performing a refresh operation. When a memory element that requires a signal for causing the memory means to perform a refresh operation is used, the refresh control means outputs a signal to the memory element for causing the memory element to perform a refresh operation. This makes it possible to use a memory element that requires an external refresh command.

[0009]

[Examples] Examples of the present invention will be shown below. FIG. 1 is a system configuration diagram showing the entire electronic device related to this embodiment. The CPU 1 is in charge of the entire system, and performs controls such as specifying addresses for writing and reading data into the memory 5 and outputting display commands to the display control device 6. The keyboard 3 is a means by which the user inputs data. The KBC 2 is a keyboard controller, and when key data is input from the keyboard 3, it sends a key code corresponding to the input key to the CPU 1. The memory 5 holds BIOS, OS, application software, etc. The memory control device 4 controls the timing of reading data from the memory 5 and writing data to the memory 5. The display control device 6 receives a display command from the CPU 1 and controls the display device 7 to perform display. The display device 7 is
Screen display is performed under the control of the display control device 6. D.M.A.
8 stands for Direct Memory Access, which is a device that directly transfers data without going through the CPU 1. When DMA8 is transferring data, C
PU1 cannot access memory. Bus 9 is the CPU
1. This is a signal line that connects the KBC 2, the memory control device 4, the memory 5, and the display control device 6, and controls signals between each device. FIG. 2 is a diagram showing the configuration of the memory control device 4 of the present invention.

Of the buses 3, the physical address bus 3a is
This is a signal line that transmits a physical address signal. A logical address signal sent from the CPU 1 is converted into a physical address signal by an address conversion device (not shown), and the memory element 5a
, 5b, 5c, address comparison devices 12a, 12b, 12
Input to c.

The memory 5 includes memory elements 5a, 5b,
Consisting of 5c. Each memory element 5a, 5b, 5c has dR
It is made of one type of semiconductor memory element among the types of semiconductor memory elements (hereinafter referred to as memory types) such as AM, SRAM, PSRAM, and ROM. Each memory element is
It is removable and can be replaced with a memory element of a different memory type or capacity.

Addressing device 11a includes memory element 5
This is a device for assigning an address to a. The user inputs from the keyboard 3 the minimum address and maximum address of the address range to be assigned to the memory element. CPU 1 sends these addresses to addressing device 11a via a data bus (not shown). Addressing device 1
1a has two registers inside, and register 1 holds the minimum address to be allocated to the memory element 5a, and register 2 holds the maximum address to be allocated to the memory element 5a. Addressing device 11a sends information held in two registers to address comparison device 12a. The addressing devices 11b and 11c also have the same function as the addressing device 11a, hold the assigned maximum address and minimum address, and send the information to the address comparison devices 12b and 12c, respectively.

The address comparison device 12a receives the minimum address and maximum address signals sent from the address designation device 11a and the physical address signal currently being accessed by the CPU 1. The address comparison device 12a is
The address capture timing is controlled by a control signal sent from. Address comparison device 12a
decodes the received signal and detects that the physical address sent from the CPU 1 is within the address range specified by the addressing device 11a, it sends the compare A signal (hereinafter referred to as COMP-A) to a high level signal ' Set to H' and output for a certain period of time. Address comparison devices 12b, 12c
The output signals will be referred to as a compare B signal (hereinafter referred to as COMP-B) and a compare C signal (hereinafter referred to as COMP-C).

The memory type register 14 is a register that holds information corresponding to the memory type of the memory elements 5a, 5b, and 5c. The memory type register 14 is 6
It consists of bits, and 2-bit information for one memory element represents the memory type of that memory element. 2-bit information representing the memory type is defined in advance. In this embodiment, "00" indicates dRAM, "01" indicates SRAM,
"10" is defined to represent PSRAM. The upper two bits of the 6-bit information held in the memory type register 14 indicate the memory type information of the memory element 5a, the next two bits indicate the memory element 5b, and the lower two bits indicate the memory type information of the memory element 5c. The memory type register 14 stores each information in the respective memory type selection devices 13a and 13b.
, send to 13c.

The memory type selection device 13a has a signal line that sends the COMP-A signal on the input side and a 2-bit signal line that sends memory type information from the memory type register 14, and a dRAM select signal line (hereinafter referred to as A signal line), SRAM select signal line (hereinafter referred to as B signal line), PS
A total of 3 bit signal lines including RAM select signal lines (hereinafter referred to as C signal lines) are connected. Also, the signal sent on the A signal line is the dRAM select signal (hereinafter referred to as the A signal), and the signal sent on the B signal line is the SRAM select signal (hereinafter referred to as the A signal).
The signal sent on the C signal line is the PSRAM select signal (hereinafter referred to as the C signal). In the memory type selection device 13a, COMP-A is a high level signal 'H'.
When the 2-bit signal sent from the memory type register 14 is received, the 2-bit signal sent from the memory type register 14 is decoded. If so, send a high level signal to the C signal line.
H' is output for a certain period of time. Memory type selection device 13b
, 13c also have the same function as the memory type selection device 13a.

The timing generator 15 receives select signals sent from the memory type selection devices 13a, 13b, and 13c, compare signals sent from the address comparators 12a, 12b, and 12c, REFS signals sent from the DMA 8, and a REFS signal sent from the CPU 1. It receives the sent CLK signal and the memory type signal of each memory element 5a, 5b, 5c from the memory type register 14, and sends a control signal to the semiconductor memory element currently being accessed. Timing generator 1
The inside of 5 is shown in FIG. 3, and will be described in detail.

The dRAM signal generator 21a, the SRAM signal generator 21b, and the PSRAM signal generator 21c are as follows:
Using the CLK signal sent from CPU1, dRA
It generates control signals for controlling M, SRAM, and PSRAM, respectively. The dRAM signal generator 21a is R
Generates and generates an AS signal, a CAS signal, and a W (write) signal. The SRAM signal generator 21b and the PSRAM signal generator 21c generate a CE (chip select) signal,
Generates and generates an OE (output enable) signal and an R/W (read/write) signal. In addition, 3 sent from the memory type selection devices 13a, 13b, 13c
The bit output signal lines are sent to the multiplexer 23 via the OR circuit 22 for each A signal line, B signal line, and C signal line.

The multiplexer 23 is an OR circuit 2 for the A signal.
If the output of B signal is a high level signal 'H', the dRAM signal generated from the dRAM signal generator 21a is used, and if the output of the OR circuit 22 of the B signal is a high level signal 'H',
If the output of the C signal OR circuit 22 is a high level signal 'H', the SRAM signal generated from the SRAM signal generator 21b is output as the PSRAM signal generated from the PSRAM signal generator 21c. . However, since only one access to the memory element 5 can be made at a time,
Two or more outputs from the three OR circuits 22 do not become high level signals 'H' at the same time. Therefore, when the memory element 5 is accessed, the multiplexer 23 always outputs a signal from one signal generator. Among the signals sent from the multiplexer 23, the RAS signal and the CE signal are sent via the same signal line (RAS/CE), and this signal is referred to as the RAST signal. The CAS signal and the OE signal are sent via the same signal line (CAS/OE), and this signal is referred to as the CAST signal. R/W signal and W
The signals are sent via the same signal line (READ/WRITE) and will be referred to as the RDWR signal.

By the way, dRAM is a semiconductor memory element that requires a memory refresh operation. Therefore, when using dRAM as a memory element, it is necessary to provide a signal for refreshing it. In this example, dRA
CAS B is one of the M memory refresh methods.
dRAM is refreshed with efore RAS Refresh. In this method, the CAS signal is
When the CAS signal falls to a low level 'L' earlier than the S signal and then remains at a low level 'L' for a certain period of time after the RAS signal falls, the dRAM enters a refresh state. In this method, the refresh address is specified within the dRAM, so there is no need to specify the address externally.

The Ref signal timing device 24a sends refresh timing signals to the memory device 5a, the Ref signal timing device 24b to the memory device 5b, and the Ref signal timing device 24c to the memory device 5c. Ref signal timing device 24a, 24
b, 24c receive the REFS signal and the memory type signal output from the corresponding memory type register 14, and if the signal is '00', the REFS signal is converted to the refresh CAS signal (REFC-A, B, C signal) and output. In addition, by passing a delay to REFC-A, B, and C, the refresh RAS signal (
REFR-A, B, C signals). This provides a refresh signal.

FIG. 4 shows a part of the timing generator, and is a diagram showing a circuit configuration for controlling each memory element using the output signal shown in FIG. 3. In FIG. FIG. 5 is a timing chart of various signals in the timing generator 15 when the CPU accesses the memory (read/write cycle) and when there is no access (refresh cycle). In this figure, it is assumed that a memory access is made to the memory element 5a, and a signal for dRAM is generated from the timing generator 15.

Since the memory element 5a was accessed, one of the address comparators 12a, 12b, and 12c is COM
A high level 'H' is sent only to PA for a certain period of time (52). The signal for dRAM is connected to the RAST signal line by RA.
It outputs the S signal (53) and the CAS (54) signal to the CAST signal line. The output RAS signal and CAS signal are inverted and input to the respective AND gates 31. C
Since the AND gate 31 inputting OMP-B and C receives the low level signal 'L', it outputs the low level signal 'L'. Since the AND gate 31 inputting COMP-A receives the high level signal 'H', the inverted signal of the RAST signal is at the high level 'H'.
', outputs a high level 'H' (60). O
When the memory is accessed, the R gate 32 outputs REFR.
- Since the high level signal 'H' (56) is always received from A, B, and C, the output of the OR gate 32 is the AND gate 3.
The output will be the same as from 1. When the output signal of this OR gate 32 is inverted (61), a signal identical to the signal generated from the timing device 15 is obtained. This allows a control signal for memory access to be sent only to the memory element 5a. Similar processing is performed even if other memory elements are accessed.

Next, when there is no access to the memory element (
In the refresh cycle, COMP-A, B, and C all become low level signals 'L' (52), so low level signals 'L' (57, 59) are all sent from the AND gate. Therefore, the signals from REFR-A, B, and C and the signals from REFC-A, B, and C are directly input to the memory element as control signals. In this embodiment, the refresh control signal is a refresh CAS signal and a RAS signal only for REFR-A and REFC-A, so the refresh signal is sent only to the memory element 5a. Refreshing is performed in this way. Next, a case will be described in which the type of memory element is replaced.

dR attached to the memory element 5a
When replacing AM with SRAM, first the replaced S
In order to allocate memory according to the storage capacity of the RAM, input the minimum address and maximum address using the keyboard 3. This input data is held in a register in the addressing device 11a from a data bus via the CPU 1. Further, a memory type is input using the keyboard 3 ('01' in this case), and this data is held in the upper two bits of the memory type register 14 from a data bus (not shown) via the CPU 1. By simply changing the values of the above registers, when the memory element 5a is accessed, the timing generator 15 sends the SRAM signal (
CE, OE, W/R) can be output to control the memory element 5a. Furthermore, since the information held in the memory type register 14 indicates SRAM, the refresh timing control device continues to output a high level, and this signal has no meaning.

Even when changing to PSRAM, it is possible to control memories of different capacities and types simply by inputting information on the memory to be used to the addressing device 11a and memory type register 14.

Note that in this embodiment, Toshiba's dRAM T
C514256, Toshiba SRAM TC551001
, Toshiba's PSRAM TC518128 is targeted as a memory element, but signal generators for various memory types are set in the timing generator 15, and the circuit is changed to allow selection by a multiplexer to correspond to the connector of the memory element. By using this interface, it is possible to support a wider variety of memory types.

As described above, in order to replace the memory element with a different memory type or add memory elements,
There is no need to redesign, and the user can easily change the memory element depending on the intended use, even if the memory element requires a refresh operation.

[0028]

According to the memory control device of the first aspect of the present invention, the type of memory used can be changed depending on the purpose of use. Further, the second invention of the present application can also be applied to a memory element that requires an external refresh command.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram showing the entire electronic device according to the present embodiment.

FIG. 2 is a diagram showing the internal configuration of the memory control device of the present invention.

FIG. 3 is a diagram showing in detail the first half of the processing part of the timing generator 15.

FIG. 4 is a diagram illustrating a circuit that is the latter half of the processing part of the timing generator, inheriting the signals from FIG. 3 and converting the signals in order to control each memory element.

FIG. 5 is a timing chart when a dRAM signal is generated from the timing generator 15 for memory access to the memory element 5a.

[Explanation of symbols]

1 CPU 2 KBC 3 Keyboard 4 Memory control device 5 Memories 5a, 5b, 5c Memory element 6 Display control device 7 Display device 8 Direct Memory Access
ss9 bus 11a, 11b, 11c addressing device 12
a, 12b, 12c address comparison device 13a,
13b, 13c memory type selection device 14
Memory type register 15 Timing generator 21a dRAM signal generator 21b SRAM signal generator 21c PSRAM signal generator 23
multiplexer

Claims (2)

[Claims] 1. A memory control device that controls a plurality of types of storage elements using different control signals, comprising a storage type holding unit that holds information representing the type of connected storage element;
A memory control device comprising: timing generation means for outputting a control signal corresponding to the connected storage element based on information held by the storage type holding means. 2. The memory control device according to claim 1,
Referring to the information held in the memory type holding means,
A memory control device characterized in that, when this information indicates a storage element that requires refreshing, refresh control means performs refresh control on the storage element that requires refreshing.