JPH01261761A - Computer system - Google Patents

Abstract

PURPOSE:To optionally and rapidly read out a basic I/O system (BIOS) programs from a RAM and to control the program by providing the title device with a memory access control means for converting a ROM access request into a RAM access. CONSTITUTION:A BIOS program writing means 1 writes BIOS programs read out from a read-only memory (ROM) 2 successively from a prescribed address of the RAM 3. After ending the BIOS program writing in the RAM 3, a mask signal generating means 7 generates a mask signal for inhibiting memory access to the ROM 2. Under said state, the memory access control means 8 monitors a mask signal sending state and an address signal and converts an access request to the ROM 2 into a prescribed address access request to the RAM 3 to read out the BIOS programs stored in the RAM 3. Consequently, the BIOS programs can be optionally and rapidly read out from the RAM 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a computer device, and particularly relates to a device for controlling the startup of a BIOS system that controls input/output devices connected to the computer device. .

[Prior Art] Conventionally, in this type of computer device, a B I OS (Basic I OS) stored in a storage medium such as a ROM is used.
nput 0output System) Reads the program and controls human output.

Then, when the power is turned on, the CPU loads the BI on the ROM.
Outputs the OS program storage address and executes reading of the BIOS program.

However, since the ROM access time is longer than the minimum cycle time of the CPU, a wait cycle is inserted into the CPU to adjust the ROM access time.

[Problem to be solved by the invention]

In this way, when the CPU reads the BIOS program in conventional computer equipment, it is necessary to insert a wait state, which inhibits the CPU's minimum cycle processing and greatly improves the efficiency of data processing through high-speed access. There was a problem that caused the performance to deteriorate.

Incidentally, even if this type of problem is attempted to be improved by using a high-speed access type ROM, the price of the ROM is extremely high, which causes an increase in the total cost.

This invention was made to solve the above problems, and when a read access of a BIOS program stored at a predetermined address in a ROM occurs, a high-speed access type RA
Write the BIOS program from the specified address of M,
It is an object of the present invention to provide a computer device that can read and control a BIOS program from a RAM at high speed at any time without changing a ROM access address by changing a ROM access request that occurs thereafter to a RAM access.

[Means to solve the problem]

A computer device according to the present invention includes a random access memory that stores a basic input/output program stored in a read-only memory from a predetermined address, and a basic input/output program that writes a basic input/output program read from the read-only memory from a predetermined address of the random access memory. input/output program writing means; and mask signal generation means for generating a mask signal for prohibiting memory access to the read-only memory after the six stages of basic input/output program writing means have finished writing the basic input/output program to the random access memory. and memory access control means for converting the read-only memory access request into a predetermined address access request for the random access memory based on the mask signal sending state and address signal output from the mask signal generation means. be.

[Operation] In this invention, the basic input/output program read from the read-only memory by the basic input/output program writing means is sequentially written from a predetermined address in the random access memory, and the writing of the basic input/output program to the random access memory is completed. Then, the mask signal generating means generates a mask signal that prohibits memory access to the read-only memory. Under this state, the memory access control means monitors the mask signal sending state and the address signal, converts the read-only memory access request into a predetermined address access request for the random access memory, and converts the read-only memory access request into a predetermined address access request for the random access memory. Executes basic input/output program reading.

〔Example〕

FIG. 1 is a block diagram illustrating the configuration of a computer device showing an embodiment of the present invention, in which 1 is a CPU circuit;
Consists of a CPU and its peripheral circuits, and handles read signals,
Outputs write signals, address signals, etc. 2 is a ROM that stores the basic input/output program (Basic Input 0
output System), for example address FOO
It is stored in correspondence with OO-FFFFF. 3 is RAM
It consists of an area E1 that stores the basic input/output program stored in the ROM 2 and an area E2 that functions as a work area for the CPU circuit 1.The area E1 is assigned an address of 00000-DFFFF, and the area E2 is assigned an address of EOOOO. -FOOOO is pre-allocated.

4 is a memory read signal, which is output from the CPU circuit 1 to the AND gate 5. A mask signal 6 is inputted to the AND gate 5 from a mask signal generator 7 serving as a mask signal generating means of the present invention, and a memory read signal 4 (memory access request) is generated by ANDing the mask signal 6 and the memory read signal 4. Sending to ROM2 is prohibited.

Reference numeral 8 denotes a RAM address controller serving as a memory access control means of the present invention, which monitors the address signal on the address bus 9 and detects whether the contents of the address are FOOOO-FFFF, for example.
In case of F, address line A16 is set to L level,
The content of the address is F 0000-'F F F F F
In other cases, the content of the address line Ale output by the CPU circuit 1 is directly output as address information of the RAM 3. This changes the content of the address to FOOOO-F
In the case of FFFF, the address line AI8 becomes L level, so the content of the address is changed to EOOOO-EFFFF.

Note that the CPU circuit 1 also serves as a basic input/output program writing means of the present invention, and the CPU circuit 1 also serves as a basic input/output program writing means of the present invention, and the
Access O-FFFFF, read the basic input/output program, and read the address E0000-FOOO of RAM3.
After writing is completed, an instruction to set the mask signal 6 to L level is output to the mask signal generator 7.

FIG. 2 is a schematic diagram illustrating the memory map changing process of the RAM 3 shown in FIG. 1, and the same parts as in FIG. 1 are given the same reference numerals.

(a) corresponds to a memory mapping state in which the mask signal 6 is at an H level, and (b) corresponds to a memory mapping state in which the mask signal 6 is at an L level.

First, while referring to Figure 2, RA the BIOS program.
The write process to M3 will be explained.

First, after the power is turned on, the CPU circuit 1 receives the memory read signal 4.
is set to H level, and outputs an instruction signal to set mask signal 6 from mask signal generator 7 to H level.

As a result, as shown in FIG. 2(a), addresses FOOOO-FFFFF of ROM2 are accessed, and the ROM
2, reads the BIOS program stored in the CPU
Address EOOOO outputted by circuit 1 to address bus 9
-Write to area E2 of RAM3 according to EFFFF.

Next, the CPU circuit 1 outputs an instruction signal to set the mask signal 6 from the mask signal generator 7 to the L level. As a result, the memory read signal 4 from the AND gate 5 is R
Since it is output to OM2, ROM2 from CPU circuit 1
Access to is prohibited.

Here, the RAM address controller 8 monitors the address output by the CPU circuit 1 onto the address bus 9.

However, if the content is FOOOO-FFFFF and the mask signal 6 from the mask signal generator 7 is at the L level, the address line AI6 is forcibly set at the L level.

As a result, even if the CPU circuit 1 outputs the address FOOOO-FFFFF for the ROM 2 to the address bus 9, the RAM address controller 8 controls the access to the address for the area E2 of the RAM 3, that is, the address EOOO
Since the request is converted into a memory access request for O-EFFFF, a hardware configuration is created that virtualizes the memory mapping shown in FIG. 2(b).

In the above embodiment, when disconnecting the ROM2 from the CPU circuit 1, this was achieved by prohibiting the sending of the memory read signal 4, but the address output from the CPU circuit 1 is decoded to send the chip select signal to the ROM2. R
A similar effect can be expected with a configuration that prohibits sending to OM2.

FIG. 3 is a flowchart illustrating an example of RA access processing according to the present invention. Note that (1) to (11) indicate each step. First, wait for the power to be turned on. 1) When the power is turned on, set the memory read signal 4 to H level, that is, to "1". (2). Next, the mask signal 6 is set to "1" (3). This enables access to the ROM2, and the CPU circuit 1 reads out the BIOS program stored in the ROM2 and starts writing it to addresses EOOOO-EFFFF in the RAM3. Next, wait for the BIOS program to finish writing.
), when writing is completed, the mask signal 6 is set to "0" (5), and access to the ROM 2 from the CPU circuit 1 is prohibited (6).

Then, the RAM address controller 8 reads the address (F), and its contents become the address FOOO for the ROM2.
Please judge whether it is O-FFFFF8), YES
If so, the address line AIe should be forcibly set to L level9), and the address 1″0000-FFF for ROM2 should be set.
A memory access request to FF is sent to RAM3 address EO.
The request is changed to a memory access request to OOO-EFFFFF (10), and the process moves on to other processing.

On the other hand, if the determination in step (8) is NO, the RAM 3 is accessed using the specified address (11), and the process moves on to other processing.

〔Effect of the invention〕

As explained above, the present invention includes a random access memory that stores a basic input/output program stored in a read-only memory from a predetermined address, and a random access memory that writes a basic input/output program read from the read-only memory from a predetermined address of the random access memory. basic input/output program writing means; mask signal generating means for generating a mask signal for prohibiting memory access to the read-only memory after the basic input/output program writing means finishes writing the basic input/output program to the random access memory; Since the memory access control means converts an access request of the read-only memory into a predetermined address access request of the random access memory based on the mask signal sending state and the address signal output from the mask signal generation means, the read-only memory It is possible to configure hardware that makes a memory access request to the storage address of a basic input/output program stored in memory a memory access request to the storage address of a basic input/output program stored in random access memory, and the basic input/output program stored in read-only memory can be configured. Basic input/output program startup can be controlled without changing the storage address of the input/output program, and the basic input/output program can be written into random access memory without changing the memory map configuration of the read-only memory.

Therefore, without changing the ROM access address,
This provides an excellent effect of constructing an inexpensive computer system that can read and control BIOS programs from RAM at high speed at any time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the configuration of a computer device showing an embodiment of the present invention, FIG. 2 is a schematic diagram illustrating the RAM memory map changing process shown in FIG.
The figure is a flowchart illustrating an example of RA access processing according to the present invention. In the figure, 1 is a CPU circuit, 2 is a ROM, 3 is a RAM, 4 is a memory read signal, 5 is an AND gate, 6 is a mask signal, 7 is a mask signal generator, 8 is a RAM address controller,
9 is an address bus. Figure 1

Claims (1)

[Claims] A computer device that reads a basic input/output program stored in a read-only memory and processes input/output data, comprising: a random access memory that stores the basic input/output program stored in the read-only memory from a predetermined address; basic input/output program writing means for writing the basic input/output program read from the only memory from a predetermined address of the random access memory; and after the basic input/output program writing means finishes writing the basic input/output program to the random access memory, the reading A mask signal generation means for generating a mask signal for prohibiting memory access to the read-only memory; and a random access request for accessing the read-only memory based on the mask signal transmission state and address signal output from the mask signal generation means. A computer device comprising: memory access control means for converting into a predetermined memory address access request.