JPS60241135A - Address producing system - Google Patents

Abstract

PURPOSE:To attain a dynamic change of the address generating method by providing a field for designation of start address, an address register and a mode bit for control of the number of bits to be effective for an instruction counter to a segment descriptor word register. CONSTITUTION:Descriptor registers 30 and 40 for segments of instruction and data includes bound fields 31 and 41, flag fields 32 and 42, mode bits 33 and 43, and base fields 34 and 44. The segment start addresses are designated at fields 34 and 44, and the number of bits to be effective are designated by the bit 33 for an instruction counter (not shown in the figure) and an address register 61. Then the contents of effective bits of the field 34 and the instruction counter are added to designate an instruction word address. While the contents of the field 34 and the register 61 and the instruction word address are added to designate a data address. Thus a conventional program can be used as a subroutine even for a new program.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an address generation method, and more particularly to a memory address generation method that dynamically changes the generation of memory addresses in a data processing system. 2. Description of the Related Art In data processing systems, large-capacity memories are now available, and in the market, demands for large-capacity memories are becoming increasingly strong. However, increasing memory capacity in a data processing system requires expanding the ability to address the memory, which changes visibility to software. As a result, programs that were compatible with traditional data processing systems cannot be used with extended data processing systems that have the ability to address large amounts of memory, and the impact is enormous. be.

In order to avoid the above problems, conventional data processing systems that change this type of functionality have had their hardware equipped with both the new functionality and the existing functionality that allows the execution of existing programs. This was a method of specifying which function to use when starting up the system. According to this method, once the system is started up, only programs that correspond to the specified functions can be used. However, due to the structure of the program, it is common for a newly developed program to use an existing program as a subroutine, and a program developed for a new function may only be executed using the existing function. A major drawback was that possible programs could not be used as subroutines.

Purpose of the Invention The present invention provides an address generation method for a data processing system that dynamically changes the memory address generation method in a data processing system, thereby making it possible to simultaneously execute programs compatible with multiple address generation methods. is intended to provide.

Another object of the present invention is to provide a memory address generation scheme for a data processing system that can expand memory address capabilities without significantly impacting software.

Structure of the Invention The memory address generation method according to the present invention includes a memory storing a segment descriptor word defining a segment including an instruction word and data, an instruction word register storing an instruction word including an address, and a segment descriptor word. A method for generating addresses of instruction words and data in a memory in a data processing system having a segment descriptor word register for storing a segment descriptor word, and an instruction counter and an address register for specifying addresses of instruction words and data in the memory, respectively. , its characteristics are that the segment descriptor word register has a base field that specifies the start address of the segment, a bound field that specifies the size of the segment, and the number of bits that should be valid in the address register and instruction counter. The address of the instruction word to be executed in memory is specified by the result of adding the contents of the base field and the valid bit of the instruction counter, and the contents of the base field and the valid bit of the address register are specified. The reason is that the address of the data in the memory is specified by the result of adding the contents of the bit and the address in the instruction word register.

The present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram of an example of a data processing system to which the present invention can be applied, and a memory device 1 stores commands and data necessary for program execution. Arithmetic device 2 reads commands and data from memory device 1 and executes a program. The input/output control device 3 controls data transfer between the memory device 1 and the input/output devices 4, 5, and 6.

FIG. 2 shows the relationship between segments in memory device 1 and segment descriptor registers 30 in arithmetic unit 2.

An instruction segment 20 containing an instruction word is defined by a segment descriptor word, which is held in an instruction segment descriptor register 30. The instruction segment descriptor register 30 consists of a bound field 31, a flag field 32, a mode bit 33, and a base field 34. A 36-bit base field 34 specifies the base address of the instruction segment 20 in word units.

A 20-bit bounds field 31 specifies the size of the instruction segment 20. The flag field 32 gives segment attributes such as execution permission and write permission to the instruction segment 20. Mode bit 33 specifies how to generate an address for memory device 1 and also specifies expansion of bounds field 31.

A data segment 21 containing data is defined by a segment descriptor word, and the segment descriptor word is held in a data segment descriptor register 40. The data segment descriptor register 40 has a bound field 41
and flag field 42 and mode bit designation flag 43
and a base field 44. The 36-bit base field 44 specifies the base address of the data segment 21 in word units. bound field 41
specifies the size of the data segment 21. Mode bit 33 in the instruction segment descriptor register specifies this bounds field 41 extension. The flag field 42 gives segment attributes such as read permission and write permission to the data segment 21 . Mode bit 43 in data segment descriptor register 40 has no meaning and is ignored. Instruction segment descriptor register 30 and data segment descriptor register 40 are loaded with segment descriptor words in memory device 1 by instructions.

FIG. 3 shows an example of an instruction register 50 that holds instruction words used in the present invention. The instruction register includes an address field 51, an instruction code 52, a data segment descriptor register designation flag 53, and an address register designation field 54.

The 18-bit address field 51 specifies the address of data within the memory device 1 in word units. The instruction code 52 specifies the processing of the instruction. The data segment descriptor register specification flag 53 specifies whether to use the instruction segment descriptor register 30 or the data segment descriptor register 40 when reading data from the memory device 1. Address register specification field 5
4 designates one address register 61 of a plurality of address registers used to generate addresses for data in the memory device 1.

FIG. 4 shows a block diagram of a circuit used to generate an address for an instruction word. An instruction counter 60 that specifies the address of the instruction word to be executed by an adder 80
and the contents of base field 34 in instruction segment descriptor register 30 are added to generate the address of the instruction word. In this case, the number of valid bits in instruction counter 60 is controlled by mode bit 33 in instruction segment descriptor register 30. In addition, the instruction counter 6
The output of 0 is compared by comparison circuit 120 with the bounds field in instruction segment descriptor register 30 to see if it exceeds the segment size, and if it does, it triggers an exception handling. do. In this case, when the mode bit 33 in the instruction segment descriptor register 30 is '0'', the contents of the 20-bit bound field are compared as a word address, and when the mode bit 33 is '1'', the contents of the 20-bit bound field are compared to the expansion circuit 130. The 36-bit contents obtained by adding 16 bits of '1' to the lower part of the 920-bit bound field are compared as word addresses.

FIG. 5 shows a block diagram of a circuit used in generating addresses for data. First, the adder 90 adds the contents of the address field 51 in the instruction register and the contents of the address register 61. This added result is added by adder 110 with the contents of base field 34 in instruction segment descriptor register 30 or with the contents of base field 44 in data segment descriptor register 40 to generate the address of the data. The selection of base field 34 or base field 44 is selected by selection circuit 100 controlled by data segment descriptor register flag 53 in the instruction register. In this case, the number of valid bits in address register 61 is controlled by mode bit 33 in instruction segment descriptor register 30. Also, the address field 51 in the instruction register
The result of adding the contents of the address register 61 and the contents of the address register 61 is sent to the comparator circuit 140 to check whether it exceeds the segment size.The result is either the contents of the bound field 31 in the instruction segment descriptor register 30 or the Bound field 4 in segment descriptor register count
1 and if the size exceeds the segment size, exception handling is started. The selection of bound field 31 or bound field 41 is made by selection circuit 160 controlled by data segment descriptor register flag 53 in instruction register 50. In this case, when mode bit 33 in instruction segment descriptor register 30 is 0, the contents of the 20-bit bound field are compared as a word address, and when mode bit 33 is ttII+, expansion circuit 150
The 36-bit contents obtained by adding 16-bit It_IN to the lower part of the 20-bit bound field are compared as a word address.

A method of generating addresses for the memory device 1 using the configuration shown in FIGS. 1 to 5 will be described below with reference to FIGS. 6 to 11.

FIG. 6 shows the method of addressing an instruction word when the mode bit 33 in the instruction segment descriptor register 30 is 0'' (hereinafter, the state in which the mode bit 33 in the instruction segment descriptor register 30 is 0'') is shown. This is called non-extended address mode, and the state where mode bit 33 is to 1pp is called extended address mode). In non-extended address mode, only the lower 18 bits (bits 18-35) of the 36-bit instruction counter 60, which determine the addressing method of the instruction word to be executed, are valid, and the contents of the lower 18 bits of the instruction counter 60 and the instruction segment description are valid. The contents of the 36-bit base field 34 in the child register 30 are added to generate the address of the instruction word.

FIG. 7 shows a method of generating addresses for data in non-extended address mode. The data address method is command word 5.
Data segment descriptor register specification flag 53 in 0
(Hereinafter, the state where the data segment descriptor register flag 53 in the instruction register 50 is "0" is called instruction segment mode, and the state where the data segment descriptor flag 53 is "1" is called data segment mode. call). FIG. 7 shows a method of generating an address for data in a non-extended address mode and an instruction segment mode; in this case, data is read from the instruction segment 20. In non-extended address mode, the 3
Only the lower 18 bits (bits 18-35□=) of the 6-bit address register 61 are valid. the result,
In non-extended address mode and instruction segment mode, the contents of the 18-bit address field 51 in the instruction register 50, the contents of the lower 18 bits of the address register 61, and the 36-bit contents of the instruction segment descriptor register 30 are
The contents of the bit base field 34 are added to generate the address of the data.

FIG. 8 shows a data address generation method in the non-extended address mode and the data segment mode. In this case, data for instruction execution is read from the data segment. The contents of the 18-bit address field 51 in the instruction register 50, the contents of the lower 18 bits of the address register 61, and the 36-bit base field 44 in the data segment descriptor register 40.
is added to specify the address of the data.

FIG. 9 shows a method of generating an address for an instruction word in the extended address mode. In the extended address mode, all bits of the 36-bit instruction counter 60 that specify the address of the instruction word to be executed are valid;
The contents of the 6 bits and the contents of the 36 bit base field 34 in the instruction segment descriptor register 30 are added to produce the address of the instruction word.

FIG. 10 shows a data address generation method in the extended address mode and the instruction segment mode.

In the extended address mode, all bits of the 36-bit address register 61 specified by the address register designation field 54 in the instruction register 50 are valid. As a result, in extended address mode and instruction segment mode, the contents of the 18-bit address field 51 in the instruction register 50, the 36-bit contents of the address register 61, and the 36-bit contents of the instruction segment descriptor register 30 are
The contents of the bit base field 34 are added to generate the address of the data.

FIG. 11 shows a method of generating a data address in the extended address mode and the data sequel mode. In this case, the contents of the 18-bit address field 51 in the instruction register 50 and the 3
6-bit contents and instruction segment descriptor register 30
The contents of the base field 34 of 36 pits are added to generate the data address.

As explained above, in the embodiments shown in FIGS. 1 to 11, 256
Definition of segment in word (218 bits) 1 and generation of instruction address, data address or 64G
It is possible to define segments up to words (236 bits) and to generate instruction addresses and data addresses.

Although not described in this embodiment, it is clear that the generated address can be considered as a virtual address and converted into a real memory address by so-called paging processing. However, it is clear that this embodiment is only an example of the present invention, and that the application of the present invention is not limited to the specific cases shown in the embodiment.

Effects of the Invention As described above, according to the present invention, the generation of memory addresses can be changed by controlling registers that can be set by software instructions, and therefore the generation of memory addresses can be dynamically changed. be.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of an example of a data processing device to which the present invention can be applied, FIG. 2 is a diagram explaining the relationship between segments and segment descriptor registers, and FIG. 3 is a diagram of the instruction word used in the present invention. FIGS. 4 and 5 are block diagrams of embodiments of the present invention, and FIGS. 6 to 11 are diagrams illustrating a memory address generation method using the blocks of FIGS. 4 and 5. . Explanation of symbols of main parts 1...Memory device 30.40.50.60, 61...Register 80
, 90, 110... Adder 100, 160... Selection circuit 130, 150... Extension circuit Applicant NEC Corporation Representative Patent attorney Shin Yanagawa

Claims (1)

[Claims] a memory that stores a segment descriptor word that defines a segment that includes an instruction word and data; an instruction word register that stores an instruction word that includes an address; a segment descriptor word register that stores the segment descriptor word; and the memory. A method for generating addresses of instruction words and data in a memory in a data processing system having an instruction counter and an address register that respectively specify addresses of instruction words and data in the segment descriptor word register, A pace field that specifies a start address of a segment, a bound field that specifies a size of the segment, and a mode pit that controls the number of bits that should be valid in the address register and the instruction counter. The address of the instruction word to be executed in the memory is specified by the result of adding the contents of the pace field and the valid pit of the instruction counter, and the contents of the pace field and the valid pit of the address register are added together. The address generation method is characterized in that the address of the data in the memory is specified by the result of adding the address in the instruction word register.