JPS57185552A - Switching device for memory bank in microcomputer system - Google Patents

Switching device for memory bank in microcomputer system

Info

Publication number
JPS57185552A
JPS57185552A JP56070287A JP7028781A JPS57185552A JP S57185552 A JPS57185552 A JP S57185552A JP 56070287 A JP56070287 A JP 56070287A JP 7028781 A JP7028781 A JP 7028781A JP S57185552 A JPS57185552 A JP S57185552A
Authority
JP
Japan
Prior art keywords
channel
cpu
memory bank
select
dma controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56070287A
Other languages
Japanese (ja)
Other versions
JPS6126699B2 (en
Inventor
Seijiro Hirayama
Shinji Yamane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP56070287A priority Critical patent/JPS57185552A/en
Publication of JPS57185552A publication Critical patent/JPS57185552A/en
Publication of JPS6126699B2 publication Critical patent/JPS6126699B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To increase the system efficiency, by enabling to select and change over a memory bank individually and respectively with each channel of a CPU and a DAM controller. CONSTITUTION:In a system where the selection of a memory bank is made with a CPU or a DMA controller, each channel of the CPU and DMA controller can individually select memory banks 1 and 2 respectively and individually, and when a CPU4(or DMA controller) selects the memory bank 1, the DMA controller can select the bank 2, or inversely even if a channel of the DMA controller executes the memory access directly, other DMA channel and the CPU can select the banks freely. Thus, the switching of the memory banks with each channel of the CPU and the DMA channel can efficiently be made.
JP56070287A 1981-05-08 1981-05-08 Switching device for memory bank in microcomputer system Granted JPS57185552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56070287A JPS57185552A (en) 1981-05-08 1981-05-08 Switching device for memory bank in microcomputer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56070287A JPS57185552A (en) 1981-05-08 1981-05-08 Switching device for memory bank in microcomputer system

Publications (2)

Publication Number Publication Date
JPS57185552A true JPS57185552A (en) 1982-11-15
JPS6126699B2 JPS6126699B2 (en) 1986-06-21

Family

ID=13427111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56070287A Granted JPS57185552A (en) 1981-05-08 1981-05-08 Switching device for memory bank in microcomputer system

Country Status (1)

Country Link
JP (1) JPS57185552A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015757A (en) * 1983-07-06 1985-01-26 Fujitsu Ltd Memory control circuit
JPS6037057A (en) * 1983-08-04 1985-02-26 Fujitsu Kiden Ltd Memory store system using direct memory access

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015757A (en) * 1983-07-06 1985-01-26 Fujitsu Ltd Memory control circuit
JPS6037057A (en) * 1983-08-04 1985-02-26 Fujitsu Kiden Ltd Memory store system using direct memory access

Also Published As

Publication number Publication date
JPS6126699B2 (en) 1986-06-21

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