JPS54155737A - Memory refresh control system - Google Patents

Memory refresh control system

Info

Publication number
JPS54155737A
JPS54155737A JP6466778A JP6466778A JPS54155737A JP S54155737 A JPS54155737 A JP S54155737A JP 6466778 A JP6466778 A JP 6466778A JP 6466778 A JP6466778 A JP 6466778A JP S54155737 A JPS54155737 A JP S54155737A
Authority
JP
Japan
Prior art keywords
memory
timing
reaches
control
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6466778A
Other languages
Japanese (ja)
Other versions
JPS6048077B2 (en
Inventor
Akira Okita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP53064667A priority Critical patent/JPS6048077B2/en
Publication of JPS54155737A publication Critical patent/JPS54155737A/en
Publication of JPS6048077B2 publication Critical patent/JPS6048077B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Abstract

PURPOSE:to make it possible to secure the memory content of a memory even while a CPU stops, and to improve the use efficiency of a memory cycle by bringing the effective timing of refresh operation completely under the control of the CPU. CONSTITUTION:The timing at which after the value of cycle counter 21 in memory 2 reaches Xi, the refresh RF indication is sent to memory element 33 in memory 2 can be made to depend upon the algorithm in request selector circuit 12 in CPU1, which allows busy control circuit 11 to control this timing, but busy control information is not disturbed at all as a result of indicating a refreshed point. Further, if the RF operation to memory 2 can not be indicated, memory 2 starts the RF operation automatically at the point in time when the value of counter 21 reaches Xj.
JP53064667A 1978-05-29 1978-05-29 Memory refresh control method Expired JPS6048077B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53064667A JPS6048077B2 (en) 1978-05-29 1978-05-29 Memory refresh control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53064667A JPS6048077B2 (en) 1978-05-29 1978-05-29 Memory refresh control method

Publications (2)

Publication Number Publication Date
JPS54155737A true JPS54155737A (en) 1979-12-08
JPS6048077B2 JPS6048077B2 (en) 1985-10-25

Family

ID=13264768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53064667A Expired JPS6048077B2 (en) 1978-05-29 1978-05-29 Memory refresh control method

Country Status (1)

Country Link
JP (1) JPS6048077B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01158553A (en) * 1987-09-17 1989-06-21 Wang Lab Inc Memory controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01158553A (en) * 1987-09-17 1989-06-21 Wang Lab Inc Memory controller

Also Published As

Publication number Publication date
JPS6048077B2 (en) 1985-10-25

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