JPH08129523A - Computer system - Google Patents

Abstract

PURPOSE: To improve the throughput of the whole of a computer system constituted by connecting plural processors and plural memories to a system bus by performing parallel processings by the respective processors without making the devices complex. CONSTITUTION: The whole system is divided into two systems, whose buses are connected by a bus exchange device 11 consisting of couples of bus arbitrating circuits 18a and 18b and output circuits 19a and 19b. A bus connection request output means which output bus connection request (h) to the opposite- side bus arbitrating circuits according to data output requests (b) and (c) from their systems to the opposite-side systems buses, and an output circuit control means which output output permission signal (a) to an output circuit outputting the data on the opposite-side system bus to its system bus between a couple of output circuits according to the bus connection p request (h) from the opposite-side bus arbitrating circuit, are added to the bus arbitrating circuits 18a and 18b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system in which a plurality of systems are connected via system buses, and more particularly to a computer system in which one system can easily access the bus of the other system.

[0002]

2. Description of the Related Art In order to improve the processing efficiency of a computer,
Incorporating multiple processors in one computer system,
It is performed to cause each processor to execute parallel processing for various data.

FIG. 6 shows N for one system bus 1.
This is a computer system in which one processor 2 and one memory 3 are connected. In such a computer system, when data is input from the outside, the data can be written into the memory 3 via one system bus, so that the configuration can be simplified.

However, since one memory 3 is commonly used by a plurality of processors 2, when each processor 2 tries to access the memory 3, while another processor 2 is executing an access to the corresponding memory 3, Access is put in a wait state, and processing efficiency decreases.

In order to eliminate such inconvenience, FIG.
8, a computer system in which a plurality of processors 2 and a plurality of memories 3 are connected to one system bus 1, and a plurality of processors 2 to the plurality of system buses 1 shown in FIG. A computer system in which a plurality of memories 3 are connected has been proposed.

Further, as shown in FIG. 9, a computer system has been proposed in which a plurality of processors 2 and a plurality of memories 3 are connected by a crossbar switch circuit 4. In each case,
Each processor 2 can designate an arbitrary memory 3 and write and read data independently to another processor and another memory.

[0007]

However, as shown in FIG.
The computer systems shown in FIGS. 8 and 9 also have the following problems to be solved. That is, in the computer system shown in FIG. 7, since only one system bus 1 is used, input / output in the case of writing data to each memory 3 from the outside or in the case of reading data from each memory 3 is performed. Since the device only needs to be connected to one system bus 1, the configuration is simplified.

However, since only one system bus 1 is used, a plurality of processors 2 cannot use the system bus 1 at the same time. As a result, a wait for the end of use of the bus of another processor 2 occurs. Therefore, compared with the computer system shown in FIG. 6, the processing speed of the entire computer system is not improved even if a plurality of memories 3 are provided.

Further, a dedicated bus arbitration circuit is required in order to avoid a conflict in which one system bus 1 is used by a plurality of processors 2 at the same time. Further, in the computer system using the plurality of system buses 1 shown in FIG. 8, the probability of occurrence of competition in which the plurality of processors 2 use the system bus 1 at the same time is reduced, and the processing efficiency of the entire computer system is improved. An arbitration circuit between the buses, such as which system bus 1 each processor 1 uses next, is required. Further, it is necessary to connect two system buses 1 to each processor 2 and each memory 3, and a dual input / output circuit for each processor 2 and each memory 3 is required, which complicates the hardware configuration. The entire computer system becomes complicated, and the manufacturing cost rises significantly.

Further, in the computer system shown in FIG. 9, not only each processor 2 can access an arbitrary memory 3 via the crossbar switch circuit 4, but also other processors 2 and other memories. The access operation with respect to 3 can be accessed completely independently. Therefore, it is possible to maximize the effect of providing a plurality of processors 2 and a plurality of memories 3 and executing the processes in parallel.

However, in the crossbar switch circuit 4,
Since all the processors 2 and all the memories 3 are connected, there is a problem that the input / output circuit of the crossbar switch circuit 4 becomes complicated and the crossbar switch circuit 4 as a whole becomes complicated.

The present invention has been made in view of the above circumstances and has a simple hardware configuration by dividing the entire system into two systems and connecting the buses of each system with a bus exchange device. , A computer system capable of efficiently executing data transfer between each processor and each memory is provided.

[0013]

In order to solve the above problems, in a computer system according to the present invention, the system buses of a pair of systems in which at least one processor and memory are connected by a system bus are exchanged. The device is connected. The bus exchange device includes a pair of bus arbitration circuits corresponding to each system in the pair of systems, and a pair of data output on one system bus of each system bus to the system bus of the other system. And an output circuit.

Bus connection request output means for outputting a bus connection request to the other-side bus arbitration circuit in response to a data output request from the own-side system to the other-side system arbitration circuit for each bus arbitration circuit, Output circuit control means for outputting an output permission signal to an output circuit of the pair of output circuits which outputs data on the partner side system bus to the own side system bus in response to a bus connection request from the partner side bus arbitration circuit And are added.

According to a second aspect of the present invention, in the self-sided system for arbitrating the bus use right for the self-sided system bus of the processor and the memory of the self-sided system with respect to each bus arbitration circuit in the computer system described above. Bus arbitration means, bus connection request output means for outputting a bus connection request to the partner side bus arbitration circuit in response to a data output request from the own side system to the partner side system bus, and bus from the partner side bus arbitration circuit A bus use right prohibiting unit for prohibiting a bus use right of the processor and the memory of the own side system to the own side system bus in response to the connection request, and a pair of output circuits in response to the bus connection request from the other side bus arbitration circuit. Output the output enable signal to the output circuit that outputs the data on the other party's system bus to the own system bus It is obtained by adding an output circuit control unit that.

[0016]

In the computer system according to the first aspect of the present invention configured as above, in the normal state, since each output circuit is in the cutoff state, each system operates independently. Therefore, each processor in each system can independently perform parallel processing regardless of the operation of the other (other party) processor.

Further, for example, when the processor in one system needs to transfer (write) data to the memory in the other system, the processor in one system is set in the own system of the bus switching device. Send a data output request to the corresponding bus arbitration circuit. Then, the bus arbitration circuit sends a bus connection request to the partner side bus arbitration circuit. Upon receiving the bus connection request, the other-side bus arbitration circuit outputs an output permission signal to the output circuit that outputs the data on the other-side system bus to the own-side system bus. Therefore, when data is output to the system bus on the one side, this data is transferred to the system bus in the system on the other side.

That is, in the normal state, each processor can execute data processing in parallel independently of each other, and if necessary, the processor of one system transfers data to the memory belonging to the other system ( (Writing) becomes possible.

Therefore, the processing efficiency of the entire computer system can be improved. Further, in the invention of claim 2, each bus arbitration circuit incorporated in the bus switching device has a function of arbitrating the bus right of use for the processor of the own system and the memory for the own system bus of the memory. That is, the usage status of the system bus on the self side is constantly grasped.

When a bus connection request is input from the other-side bus arbitration circuit, the own-side system bus disables the use of the own-side processor and memory, and then the other-side system bus of the pair of output circuits. The output permission signal is output to the output circuit that outputs the above data to the system bus on the self side. That is, it is possible to prevent the data transferred from the partner system from competing on the system bus in the own system.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a schematic configuration of the computer system of the embodiment. This computer system is composed of a pair of systems 10a and 10b and a single bus switching device 11 that connects the pair of systems 10a and 10b.

In the computer system of this embodiment, one processor 12a, 12b and one memory 1 are provided in each system 10a, 10b for simplification of description.
3a and 13b are provided. And processor 1
2a, 12b and the memories 13a, 13 are connected to the data bus 14
a, 14b, address buses 15a, 15b, and control buses 16a, 16b. Data buses 14a and 14b and address buses 15a and 15b
Respectively configure system buses 17a and 17b.

For example, as shown in FIG. 1, the bus switching device 11 is composed of a pair of bus arbitration circuits 18a and 18b and a pair of output circuits 19a and 18b, which are provided corresponding to the systems 10a and 10b, respectively. Has been done.

The system bus 17a of one system 10a is connected to the input terminal of the output circuit 19a, the system bus 17b of the other system 10b is connected to the output terminal of the output circuit 19a, and this output circuit 1
When the L (low) level output permission a ₂ is input to the control terminal 9a from the other side bus tone circuit 18b, the data output on the system bus 17a of one system 10a is transferred to the other system 10b. Output to the system bus 17b.

Similarly, the input terminal of the output circuit 19b is connected to the system bus 17b of the system 10b, the output terminal of the output circuit 19b is connected to the system bus 17a of the system 10a, and the output circuit 19b is connected.
When the L level output permission a ₁ is input from the bus adjusting circuit 18a to the control terminal, the system bus 1 of the system 10b
The data output on 7b is output on the system bus 17a of the system 10a.

Bus acquisition requests b ₁ and c ₁ are individually input to the bus arbitration circuit 18a from the processor 12a and the memory 13a of the self-side system 10a. The bus arbitration circuit 18a includes the processor 1 of the self-side system 10a.
Data output requests d ₁ and e ₁ to the system bus 17b of the partner system 10b are individually input from the memory 2a and the memory 13a.

From the bus arbitration circuit 18a, a bus acquisition notification f ₁ for the bus acquisition request b ₁ and the data output request d ₁ of the processor 12a, and a bus acquisition request c ₁ and the data output request e ₁ of the memory 13a are provided. The acquisition notification g ₁ is output. Further, the bus connection request h ₁ is output from the bus arbitration circuit 18a to the other side bus arbitration circuit 18b.

The bus acquisition requests b ₁ and c ₁ , the data output requests d ₁ and e ₁ , and the bus acquisition notifications f ₁ and g ₁ are transmitted to the processor 12a, the control bus 16a shown in FIG.
Transmission / reception is performed between the memory 13a and the bus arbitration circuit 18a.

Similarly, the bus arbitration circuit 18b requests the bus acquisition requests b ₂ and c ₂ from the processor 12b and the memory 13b of the self-side system 10b and the data output requests d ₂ and e ₂ to the system bus 17a of the partner system 10a. Are entered individually.

Further, the bus arbitration circuit 18b sends a bus acquisition request b ₂ and a data output request d ₂ to the processor 12b.
Bus acquisition notification f _{2 to} the memory 13b and a bus acquisition notification g ₁ to the bus acquisition request c ₁ and the data output request e ₁ of the memory 13b are output. Further, a bus connection request h ₂ is output from the bus arbitration circuit 18b to the other side bus arbitration circuit 18a.

Next, the operation of the computer system incorporating the bus exchange apparatus 11 shown in FIG. 1 will be described with reference to the time charts shown in FIGS. Each processor 12a, 12b and each memory 13a, 13b incorporated in each system 10a, 10b of this computer system outputs a bus acquisition request in one clock cycle in synchronization with the system clock CLK having a predetermined cycle T. , The bus use right is secured in the next clock cycle, and the data to be transferred is output to the bus in this clock cycle.

In the computer system having such a basic operation, the cycle T1 of the system clock CLK shown in FIG.
At the bus acquisition request c from the memory 13a of the system 10a
_{When 1} is output to the bus arbitration circuit 18a, the bus arbitration circuit 18a confirms that the bus acquisition request b ₁ is not output from the processor 12a in the same cycle (T1), and notifies the memory 13a of the bus acquisition notification g. Sends ₁ .

Therefore, the memory 13a secures the right to use the system bus 17a in the next cycle T2, and the system bus 1a
The data is output to 7a. If necessary, the processor 12a takes in the data output to the system bus 17a in the cycle T2.

Then, when the processor 12a outputs the bus acquisition request b ₁ to the bus arbitration circuit 18a in the cycle T2,
The bus arbitration circuit 18a uses the memory 13 at the same cycle (T2).
After confirming that the bus acquisition request c ₁ is not output from a, the bus acquisition notification f ₁ is sent to the processor 12a.
Therefore, the processor 12a secures the right to use the system bus 17a and outputs the data to the system bus 17a in the next cycle T3. If necessary, the memory 13a takes in the data output to the system bus 17a at the cycle T3 and stores (writes) the data.

In the cycle T3, the processors 12a,
When the bus acquisition requests b ₁ and c ₁ are not output from the memory 13a, the system bus 17a is in the unused state in the next cycle T4.

Further, in the cycle T4, the processor 12
If the bus acquisition requests b ₁ and c ₁ are simultaneously output from the memory a and the memory 13a, the race condition occurs. In this case, the bus arbitration circuit 18a arbitrates the two, gives priority to the bus acquisition request b ₁ of the predetermined processor 12a, and sends the bus acquisition notification f ₁ to the processor 12a. Therefore,
In the next cycle T5, the processor 12a uses the system bus 17a.

Since the memory 13a has not received the bus acquisition notice g ₁ , it continues to output the bus acquisition request c ₁ even in the cycle T5. Then, in the next cycle T6, the right to use the system bus 17a is acquired and the data is output.

In this way, the bus arbitration circuit 18a arbitrates the bus use right on the system bus 17a in the self-side system 10a. Further, in the cycle T7 of FIG. 4, the bus acquisition request b ₁ and the data output request d ₁ are simultaneously issued from the processor 12a of the system 10a to the bus arbitration circuit 18.
When output to a, the bus arbitration circuit 18a sends a bus connection request h ₁ to the other side bus arbitration circuit 18a. Also,
An H (high) level bus acquisition notification f ₁ is sent to the requesting processor 12a.

Upon reception of the bus connection request h ₁ , the bus arbitration circuit 18b on the other side receives an L (low) level bus which indicates bus prohibition to the processor 12b and the memory 13b of the own side system 10b in the next cycle T8. Acquisition notification f
₂ and g ₂ are output. Further, in the same cycle T8, the L level output permission a ₂ is sent to the output circuit 19a.

As a result, in the cycle T8, the output circuit 19a has a function of outputting the data on the system bus 17a of the system 10a to the system bus 17b of the system 10b.
a of the processor 12a of both the systems 10a, 19b
The system buses 17a and 17b can be used simultaneously.

Therefore, the processor 12a can transfer data to the memory 13a of the partner system 10b or the processor 12b. In this case, as shown in FIG. 4, the memory 1 of the system 10b of the data transfer destination
3b has the same cycle T8, the bus arbitration circuit 18b sends the H level bus acquisition request c ₂ and the data output request e.
_{When 2} is output, the bus connection request h ₂ is output to the other side bus arbitration circuit 18a. However, the bus arbitration circuit 18
Since “a” is already outputting the bus connection request h ₁ , it does not respond to the bus connection request h ₂ .

Also in the bus arbitration circuit 18b, in the cycle T8, the bus connection request h ₁ from the other side bus arbitration circuit 18a is prioritized, so as described above, in the cycle T8, with respect to the memory 13b. The H-level bus acquisition notification g ₂ is not output.

Further, in the cycle T8, the system 10
When the bus acquisition request c ₁ and the data transmission request e ₁ are output from the a-side memory 13a, the bus 17b of the system 10b is being used by the processor 12a on the system 10a side in this cycle T8. 10b
Bus acquisition request c ₂ and data transmission request e of the memory 13b of
System bus 1 is given priority over ₂ in cycle T9
The right to use 7a and 17b is the memory 13 on the system 10a side.
assigned to a.

The bus acquisition request c ₂ and the data transmission request e ₂ of the memory 13b of the system 10b are realized in the period T10 next to the period T9. In the computer system configured in this way, in the normal state, the output circuits 19a and 19b are in the cutoff state, so that the systems 10a and 10b operate independently.
Therefore, the processors 12a and 12b and the memories 13a and 13b in the respective systems 10a and 10b have their own systems 10a. Within 10b, independent parallel processing is possible regardless of the operations of the processors 12b and 12a and the memories 13b and 13a of the other systems 10b and 10a.

Also, for example, one of the systems 10a, 1
0b processor 12a, 12b or memory 13a,
When it becomes necessary for 13b to transfer data to the processor 12b, 12a or the memory 13b, 13a in the other system 10b, 10a, a bus acquisition request and a bus acquisition request are sent to the bus arbitration circuit 18a, 18b on the self side of the bus switching device 11. When a data output request is sent, the self-systems 10a, 10b
System buses 17a and 17b are connected to the partner system buses 17b and 17a. Therefore, the processor 12
The data a, 12b and the memories 13a, 13b can transfer data to the processors 12b, 12a and the memories 13b, 13a of the other system 10b, 10a.

Therefore, the processing efficiency of the entire computer system can be improved. Further, each processor 12a, 12b and each memory 13a, 13b has one system bus 17
Since only a and 17b are connected, it is not necessary to mount a complicated input / output circuit for connecting to the two system buses 1 and 1 shown in FIG. Can be simplified.

Further, in the computer system of the embodiment, the bus arbitration circuits 18a, 18 in the bus switching device 11 are arranged.
b has a built-in bus arbitration function in the system that adjusts contention when the processors 12a and 12b and the memories 13a and 13b in the systems 10a and 10b on the self side use the system buses 17a and 17b. It is not necessary to separately provide a dedicated bus arbitration circuit for 10a and 10b.

FIG. 5 is a book diagram showing a schematic configuration of a computer system according to another embodiment of the present invention. In the system of this embodiment, in each of the systems 10a and 10b,
Dedicated bus arbitration circuits 20a and 20b for arbitrating contention on the system buses 17a and 17b when the systems 10a and 10b operate independently of each other are provided.

Therefore, each of the bus arbitration circuits 18a and 18b in the bus switching device 11 does not need to execute the bus arbitration of the self-side system, and the processors 12a and 12b and the memories 13a and 13b to the other-side system 10b, 10b.
It is only necessary to receive a data transmission request for a. Then, the bus states of the self-side system 10a, 10bb may be read from the dedicated bus arbitration circuits 20a, 20b described above.

The bus arbitration circuits 20a and 20b are already incorporated in a computer system in which a plurality of processors and memories are incorporated. Therefore, by utilizing the functions of the bus arbitration circuits 20a and 20b already incorporated. The configurations of the bus arbitration circuits 18a and 18b of the newly created bus exchange device 11 can be simplified.

The present invention is not limited to the system of each embodiment described above. In the system of the embodiment, one processor 12a, 12b and one memory 13a, 13 are provided in each system 10a, 10b.
b is incorporated. However, it is also possible to incorporate a plurality of processors and a plurality of memories respectively.

Further, in the computer system of the present invention, the pair of systems 10a and 10b are combined into one bus switching device 11.
However, by connecting multiple systems in series with multiple bus switching devices, N system buses 1
A larger computer system can be constructed with 7a, 17b and (N-1) bus switching devices 11.

[0053]

As described above, in the computer system of the present invention, the entire system is divided into two systems, and the buses of each system are connected by the bus switching device. The bus switching device has a function of connecting the buses to each other when data is transferred to the other system. Therefore, in the normal state, each system can perform information report processing independently of each other, and data can be transferred to the system bus of the other side only when necessary, so that the processing efficiency of the entire computer system can be greatly improved. . Moreover, since it is not necessary to make each processor and each memory a particularly complicated hardware configuration, the manufacturing cost of the entire computer system does not increase significantly.

A bus arbitration function for arbitrating contention on the system bus in the self-side system is added to each bus arbitration circuit of the bus exchange apparatus in addition to the bus connection control function for data transfer to the partner system. ing. Therefore, each system does not need to separately provide a dedicated bus arbitration circuit.
Therefore, the manufacturing cost of the entire computer system can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a bus exchange device in a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of the computer system of the embodiment.

FIG. 3 is a time chart showing the operation of the bus exchange device of the system of the embodiment.

FIG. 4 is a time chart showing the operation of the bus exchange device.

FIG. 5 is a block diagram showing the overall configuration of a computer system according to another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional computer system incorporating a plurality of processors.

FIG. 7 is a block diagram showing a conventional computer system incorporating a plurality of processors and a plurality of memories.

FIG. 8 is a block diagram showing a conventional computer system using a plurality of system buses.

FIG. 9 is a block diagram showing a computer system using a conventional crossbar switch circuit.

[Explanation of symbols]

10a, 10b ... System, 11 ... Bus exchange device, 12
a, 12b ... Processor, 13a, 13b ... Memory, 1
6a, 16b ... Control bus, 17a, 17b ... System bus, 18a, 18b ... Bus arbitration circuit, 19a, 19b ...
Output circuit, a ₁ , a ₂ ... Output permission, b ₁ , b ₂ , c ₁ ,
c ₂ ... Bus acquisition request, d ₁ , d ₂ . e ₁ , e ₂ ... Data output request, f ₁ , f ₂ , g ₁ , g ₂ ... Bus acquisition notification, h
₁ , h ₂ ... Bus connection request

Claims (2)

[Claims] 1. A computer system in which at least one processor and a memory are connected by a system bus, and the system buses are connected by a bus exchange device in a pair of systems, wherein the bus exchange device is the pair. A pair of bus arbitration circuits corresponding to each system in the system, and a pair of output circuits that outputs the data output on one system bus in each system bus to the system bus of the other system, Each of the bus arbitration circuits outputs a bus connection request to the other-side bus arbitration circuit in response to a data output request from the own-side system to the other-side system bus, and the other-side bus arbitration circuit. In response to a bus connection request from the circuit, the data on the partner system bus of the pair of output circuits is transferred to the self side. Computer system characterized by comprising an output circuit control means for outputting an output enable signal to an output circuit for outputting onto Sutemubasu. 2. A computer system in which at least one processor and a memory are connected to each other by a system bus, and each of the system buses is connected to each other by a bus exchange device, wherein the bus exchange device is the pair of systems. A pair of bus arbitration circuits corresponding to each system in the system, and a pair of output circuits that outputs the data output on one system bus in each system bus to the system bus of the other system, Each of the bus arbitration circuits arbitrates the internal system bus arbitration means for arbitrating the bus usage right of the processor and the memory of the own system for the own system bus, and the data output from the own system to the other system bus. Bus connection request output that outputs a bus connection request to the other side bus arbitration circuit according to the request And a bus use right prohibition means for prohibiting the bus use right of the processor and the memory of the own side system to the own side system bus in response to a bus connection request from the other side bus arbitration circuit, and the other side bus arbitration circuit. The output circuit control means for outputting the output permission signal to the output circuit for outputting the data on the partner side system bus to the own side system bus among the pair of output circuits. A computer system characterized by.