JPH11134287A - Input/output bus data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input/output bus data transfer device for making plural DMA (direct memory access) devices able to simultaneously obtain data on the same address of a memory. SOLUTION: An access control part 1 outputs a memory read transaction or a broadcast memory read transaction to a memory bus based on the memory address of a DMA read request from the DMA device. An FF(flip-flop) 2 holds the memory address of the DMA read request and the FF 4 holds the memory address of the DMA read request passed through a selector 3. A comparator 5 compares the memory address of a data response on the memory bus with the memory address of the FF 4. The FF 6 holds the data of the data response when a compared result matches and returns it onto an IO bus as the data response along with a value held in the FF 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output bus data transfer device, and more particularly to a main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, and a connection to the main storage device. The present invention relates to an input / output bus data transfer method for a system including a memory bus to be connected and a plurality of bridge circuits connecting a plurality of input / output buses connected to a plurality of input / output devices.

[0002]

2. Description of the Related Art Conventionally, in an I / O bus data transfer method, as shown in FIG.
memory access) device (# 1, # 2) 3
4 and 35 access the memory 30 via the IO buses # 1 and # 2, the IO-BUS bridges (# 1 and # 2) 32 and 33, the memory bus, and the memory controller 31.

In this case, when transferring the same data to the respective DMA devices 34, 35 connected to the respective IO buses # 1, # 2, the respective DMA devices 34, 35
Of the DMA devices 34 and 35 individually.
Has to issue DMA read requests separately.

[0004] That is, the DMA read requests issued from the DMA devices 34 and 35 are not broadcasted (there is no such mechanism).
The data response (response or data from the memory 30) is the DMA device 3 that has issued the DMA read request.
Only return to 4,35. As the bus control as described above, there are techniques disclosed in Japanese Patent Application Laid-Open Nos. 5-233528 and 9-44443.

[0005]

In the above-mentioned conventional I / O bus data transfer method, when transferring the same data to a plurality of DMA devices, the only option is to issue DMA read requests from the plurality of DMA devices separately. Therefore, it takes twice as much time and twice as much load in mounting disk mirroring or the like, which is a bottleneck in performance. That is,
In the conventional input / output bus data transfer method, it is impossible for a plurality of DMA devices to simultaneously obtain data on the same address of the memory.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an I / O bus data transfer device in which a plurality of DMA devices can simultaneously obtain data on the same address of a memory.

[0007]

A first input / output bus data transfer device according to the present invention includes a main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, An I / O bus data transfer device for a system comprising a memory bus connected to the main storage device and a plurality of bridge circuits connecting a plurality of I / O buses connected to the plurality of I / O devices, Requesting the main storage device to transfer data read from the main storage device to each of the plurality of input / output devices when the read request to the main storage device indicates the transfer of the same data to the plurality of input / output devices. Output means for outputting a broadcast request to be transmitted, and data provided from each of the plurality of bridge circuits and read from the main storage device at the time of outputting the broadcast request. And a plurality of transfer means for transferring the input-output device in the subordinate apparatus.

A second input / output bus data transfer device according to the present invention is connected to a main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, and connected to the main storage device. An I / O bus data transfer device for a system comprising a memory bus to be connected and a plurality of bridge circuits connecting a plurality of I / O buses connected to the plurality of I / O devices, wherein When a read address sent to the memory bus via a circuit is a predetermined specific address, transfer of data read from the main storage device to each of the plurality of input / output devices based on the read address is performed. Means for outputting a requested broadcast request, first holding means for holding a read address from the input / output device, and first holding means Second holding means for holding one of the held read address and the address of the broadcast request, an address added to the data read from the main storage device, and the second holding means Each of the plurality of bridge circuits includes a comparing unit that compares the address and a data holding unit that holds data read from the main storage device when a match is detected by the comparing unit.

A third input / output bus data transfer device according to the present invention is connected to a main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, and connected to the main storage device. I / O bus data transfer device for a system comprising a memory bus to be connected and a plurality of bridge circuits connecting a plurality of I / O buses connected to the plurality of I / O devices, First holding means for holding a read address sent from the input / output device, and when the read address held in the first holding means is a predetermined specific address, the first holding means stores the read address based on the read address. Access control means for outputting a broadcast request for requesting transfer of data read from the main storage device to each of the plurality of input / output devices;
Second holding means for holding one of the read address held in the first holding means and the address of the broadcast request; and an address added to the data read from the main storage device and the second Comparing means for comparing the address held in the holding means, and data holding means for holding data read from the main storage device when a match is detected by the comparing means, for each of the plurality of bridge circuits. Have.

A fourth input / output bus data transfer device according to the present invention is connected to a main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, and a connection to the main storage device. An I / O bus data transfer device for a system comprising a memory bus to be connected and a plurality of bridge circuits connecting a plurality of I / O buses connected to the plurality of I / O devices, wherein When a read address sent to the memory bus via a circuit is a predetermined specific address, transfer of data read from the main storage device to each of the plurality of input / output devices based on the read address is performed. Means for outputting a broadcast request to be requested, first storage means for sequentially storing read addresses from the input / output device, and the first storage A second storage unit for sequentially storing one of the read address and the broadcast request address held in a row, an address added to data read from the main storage device, and a second storage unit. Each of the plurality of bridge circuits is provided with a comparing unit for comparing the stored address and a data storing unit for sequentially storing data read from the main storage device when a match is detected by the comparing unit. .

A fifth input / output bus data transfer device according to the present invention includes a main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, and a connection to the main storage device. An I / O bus data transfer device for a system comprising a memory bus to be connected and a plurality of bridge circuits connecting a plurality of I / O buses connected to the plurality of I / O devices, wherein When the identification information for identifying the read request sent to the memory bus via the circuit is specific identification information set in advance, the plurality of input data read from the main storage device based on the identification information is stored. Means for outputting a broadcast request requesting transfer to each output device, first holding means for holding identification information from the input / output device, and first holding Second holding means for holding one of the identification information held in a row and the identification information of the broadcast request; identification information added to data read from the main storage device; and the second holding means. Comparing means for comparing the identification information held in the plurality of bridge circuits, and data holding means for holding data read from the main storage device when a match is detected by the comparing means. I have.

A sixth input / output bus data transfer device according to the present invention includes a main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, and a connection to the main storage device. I / O bus data transfer device for a system comprising a memory bus to be connected and a plurality of bridge circuits connecting a plurality of I / O buses connected to the plurality of I / O devices, First holding means for holding identification information for identifying a read request sent from the input / output device, and when the identification information held in the first holding means is predetermined specific identification information, Access control means for outputting a broadcast request for requesting transfer of data read from the main storage device to each of the plurality of input / output devices based on the identification information; Second holding means for holding one of the identification information held by the means and identification information of the broadcast request; identification information added to data read from the main storage device; and the second holding means. Comparing means for comparing the identification information held in the plurality of bridge circuits, and data holding means for holding data read from the main storage device when a match is detected by the comparing means. I have.

That is, the input / output bus data transfer device of the present invention transfers data to two different IO buses simultaneously, thereby realizing disk mirroring and simultaneous double transfer of image display data, network data, and the like. Is what you do.

DMA issued from DMA device # 1
The read request is issued as a split transaction as a feature of the present invention. The transaction of the DMA read request is converted into a transaction on the memory bus via the IO-BUS bridge # 1.

The converted transaction includes a broadcast memory read transaction, which is a feature of the present invention, in addition to a conventional normal memory read transaction.
May be converted to a transaction. Separation of these two transactions is IO-BUS bridge # 1
It depends on the setting.

According to the memory read transaction, the memory controller acquires data from the memory and issues a data response transaction to the memory bus. When a broadcast memory read transaction is issued to the memory bus, Is configured so that all the IO-BUS bridges # 1 and # 2 connected on the memory bus receive a data response thereto.

That is, in the case of this example, a normal memory
In a read transaction, the IO-BU that is the issuer
While only the S-bridge # 1 receives the data response, in the case of the broadcast memory read transaction, all the IO-BUS bridges #
1 and # 2 receive the data response.

Thus, a plurality of DMA devices #
1 and # 2 can simultaneously obtain data on the same address in the memory via separate IO-BUS bridges # 1 and # 2.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an IO-BUS (input / output bus) bridge according to one embodiment of the present invention. In the figure, the IO-BUS bridge includes an access control unit 1, flip-flops (hereinafter, referred to as FFs) 2, 4, and 6, a selector 3, and a comparator 5.

A DMA (Direct Memo) not shown
ry Access) DMA accepted from the device
The memory address of the read request is held in the FF 2 and is used when the access control unit 1 issues a memory read transaction to a memory bus (not shown).

At the same time, the address value of FF2 is held in FF4 via selector 3. When a data response is issued from a memory control device (not shown) on the memory bus, the FF 4 is used to compare whether the data response corresponds to a memory read transaction issued by the own device. I do.

That is, the data response also includes the memory address information of the corresponding memory read transaction. The address of the data response is compared with the value of FF4 by the comparator 5, and if they match, the data of the data response is held in the FF6 and an IO (not shown)
It is returned as a data response on the bus. The address at that time uses the value held in FF4.

When a broadcast memory read transaction is issued from the access control unit 1 onto the memory bus, the address information is held in the FF 4 from the memory bus via the selector 3.

Note that, as an example, the access control unit 1 is an FF
2, a broadcast memory read transaction is issued when the address is within a specific DMA address area set in advance.

As a result, the data response corresponding to the broadcast memory read transaction is transmitted to all the IO-BUSs connected to the memory bus.
The bridge can receive.

Here, in one embodiment of the present invention, similarly to the conventional example, a system configuration as shown in FIG. 6 is adopted, and IO-BUS bridges (# 1, # 2) 32, 3
3 has a configuration as shown in FIG.

In FIG. 6, the DMA device (# 1) 3
4 is issued from the access control unit 1 of the IO-BUS bridge 32 as a split transaction. The transaction of the DMA read request is converted into a transaction on the memory bus via the IO-BUS bridge 32.

The converted transaction may be converted to a broadcast memory read transaction as described above, in addition to a normal memory read transaction as in the past. The separation of these two transactions depends on the setting of the access control unit 1 of the IO-BUS bridge 32.

In response to the memory read transaction, the memory controller 31 obtains data from the memory 30 and issues a data response transaction to the memory bus, but a broadcast memory read transaction is issued on the memory bus. In this case, a data response to the request is received by all the IO-BUS bridges 32 and 33 connected to the memory bus.

That is, in the case of this example, the normal memory
In a read transaction, the IO-BU that is the issuer
While only the S bridge 32 receives the data response, in the case of the broadcast memory read transaction, the IO-BUS bridge 32, 33
Receives the data response.

FIG. 2 is a diagram showing the temporal correlation of transactions on each bus according to one embodiment of the present invention. The processing operation according to the embodiment of the present invention will be described with reference to FIGS. 1, 2 and 6.

First, when the DMA read request A1 is issued from the DMA device 32, the IO-BUS bridge 32
If the address of the DMA read request A1 is within a specific DMA address area, the access control unit 1
An MA read request A1 is issued on the memory bus as a broadcast memory read transaction A2. At this time, the F of each of the IO-BUS bridges 32 and 33
F4 holds the address of the DMA read request A1.

[0033] The memory controller 31 broadcasts
A data response A3 corresponding to the memory read transaction A2 is issued. This data response A
3 is received by each of the IO-BUS bridges 32 and 33, the data response A is transmitted from each of the IO-BUS bridges 32 and 33 onto each of the IO buses # 1 and # 2.
4, A5 are issued simultaneously.

Thus, with a single request instruction,
Since the same transaction can be issued to a plurality of different buses (IO bus # 1 and IO bus # 2),
Mounting such as disk mirroring becomes easy. That is, the plurality of DMA devices 34 and 35 can simultaneously obtain data on the same address of the memory 30.

FIG. 3 shows an IO-B according to another embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a US bridge. In the figure, an IO-BUS bridge according to another embodiment of the present invention uses a transaction number instead of an address.

That is, an IO according to another embodiment of the present invention
A BUS bridge includes an access control unit 11, an FF 12,
14, 16, a selector 13, and a comparator 15. The other embodiment of the present invention has a system configuration as shown in FIG. 6 similarly to the embodiment of the present invention, and the IO-BUS bridges 32 and 33 shown in FIG.
The configuration is as shown in FIG.

The transaction number of the DMA read request received from the DMA devices 34 and 35 is FF12
And is used when the access control unit 11 issues a memory read transaction on the memory bus.

At the same time, the transaction number of the FF 12 is held in the FF 14 via the selector 13. FF1
Reference numeral 4 is used when a data response is issued on the memory bus from the memory control device 31 to compare whether or not the data response corresponds to a memory read transaction issued by the own device.

That is, the data response also includes the transaction number of the corresponding memory read transaction. The transaction number of the data response is compared with the value of the FF 14 by the comparator 15, and when they match, the data of the data response is held in the FF 16 and returned as a data response on the IO bus # 1, # 2. The transaction number at that time is F
The value held in F14 is used.

When a broadcast memory read transaction is issued from the access control unit 11 on the memory bus, the transaction number is held in the FF 14 from the memory bus via the selector 13.

Incidentally, as an example, the access control section 11
On the basis of the transaction number held in F2, a broadcast memory read transaction is issued when the transaction number is a transaction number for a predetermined DMA address area set in advance.

As a result, the data response corresponding to the broadcast memory read transaction is transmitted to all the IO-BUSs connected to the memory bus.
Bridges 32 and 33 can receive.

FIG. 4 is a diagram showing the temporal correlation of transactions on each bus according to another embodiment of the present invention.
A processing operation according to another embodiment of the present invention will be described with reference to FIGS. 3, 4, and 6.

First, when the DMA read request B1 is issued from the DMA device 32, the IO-BUS bridge 32
If the transaction number of the DMA read request B1 is a specific transaction number, the access control unit 11 issues the DMA read request B1 on the memory bus as a broadcast memory read transaction B2. At this time, the IO-BUS bridges 32, 3
3 Each FF 14 holds the transaction number of the DMA read request B1.

The memory controller 31 broadcasts
A data response B3 corresponding to the memory read transaction B2 is issued. This data response B
3 is received by each of the IO-BUS bridges 32 and 33, the data response B is transmitted from each of the IO-BUS bridges 32 and 33 onto each of the IO bus # 1 and the IO bus # 2.
4, B5 are issued simultaneously.

Thus, with a single request instruction,
Since the same transaction can be issued to a plurality of different buses (IO bus # 1 and IO bus # 2),
Mounting such as disk mirroring becomes easy. That is, the plurality of DMA devices 34 and 35 can simultaneously obtain data on the same address of the memory 30.

FIG. 5 shows an IO-B according to another embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a US bridge. In the figure, an IO-BUS bridge according to another embodiment of the present invention can hold a plurality of addresses.

That is, an IO according to another embodiment of the present invention
-The BUS bridge connects the access control unit 21 and the FIFO
(First-In First-Out) 22,2
4, 26, a selector 23 and a comparator 25. In addition, another embodiment of the present invention has a system configuration as shown in FIG. 6 similarly to the embodiment of the present invention.
The IO-BUS bridges 32 and 33 shown in FIG. 6 have a configuration as shown in FIG.

The memory address of the DMA read request received from the DMA devices 32 and 33 is
Are sequentially stored and used when the access control unit 21 issues a memory read transaction onto the memory bus.

At the same time, the address value stored in the FIFO 22 is held in the FIFO 24 via the selector 23. The FIFO 24 is used when a data response is issued from the memory controller 31 on the memory bus to compare whether or not the data response corresponds to a memory read transaction issued by the own device.

That is, the data response also includes the memory address information of the corresponding memory read transaction. The address of the data response is compared with the value of the FIFO 24 by the comparator 25, and if they match, the data of the data response is held in the FIFO 26 and returned as a data response on the IO bus.
The address at that time uses the value held in the FIFO 24.

When a broadcast memory read transaction is issued from the access control unit 21 on the memory bus, the address information is held in the FIFO 24 via the selector 23 from the memory bus.

Note that, as an example, the access control unit 21
Based on the address held in the IFO 22, a broadcast memory read transaction is issued when the address is within a specific DMA address area set in advance.

As a result, the data response corresponding to the broadcast memory read transaction is transmitted to all the IO-BUSs connected to the memory bus.
Bridges 34, 35 can receive. As described above, by allowing a plurality of addresses to be stored in the FIFOs 22, 24, and 26, it becomes possible to issue a plurality of transactions, and such a configuration is more advantageous in terms of performance in practical use.

The memory read transaction or the broadcast memory read transaction is issued not only by the IO-BUS bridges 32 and 33 but also by, for example, a main processor device (not shown) connected to a memory bus. It is also possible.

In this case, the DMA read request A shown in FIG.
1 or the transaction of the DMA read request B1 shown in FIG. 4 is omitted, and the broadcast processor shown in FIG.
Read transaction A2 or broadcast memory read transaction B2 shown in FIG.
Is issued. The data response to this is received by the IO-BUS bridges # 1 and # 2.

As described above, the DMA read request issued from the DMA device # 1 is transmitted to the access control units 1, 11, and 12.
1 to the memory bus as a normal memory read transaction or a broadcast memory read transaction, and when the memory controller 31 outputs a data response to the broadcast memory read transaction to the memory bus, Are received by the IO-BUS bridges 32 and 33 and transferred to the plurality of DMA devices 34 and 35, so that the plurality of DMA devices 34 and 35
Data on the same address of the memory 30 can be obtained simultaneously via the US bridges 32 and 33.

[0058]

As described above, according to the present invention, a main storage device, a plurality of input / output devices for transferring data to and from the main storage device by direct memory access, and a memory connected to the main storage device In an input / output bus data transfer device of a system comprising a bus and a plurality of bridge circuits connecting a plurality of input / output buses connected to a plurality of input / output devices, a read request to a main storage device is transmitted to a plurality of input / output devices. A broadcast request for requesting the main memory to transfer the data read from the main memory to each of the plurality of input / output devices when indicating the transfer of the same data to the main memory; By transferring the data read from each of the plurality of bridge circuits to the I / O device under its own device, the plurality of I / O devices Data there is an effect that can be obtained simultaneously.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an IO-BUS bridge according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating the temporal correlation of transactions on each bus according to one embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of an IO-BUS bridge according to another embodiment of the present invention.

FIG. 4 is a diagram illustrating the temporal correlation of transactions on each bus according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an IO-BUS bridge according to another embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of an input / output bus data transfer system.

[Explanation of symbols]

 1,11,21 access control unit 2,4,6,12,14,16 flip-flop 3,13,23 selector 5,15,25 comparator 22,24,26 FIFO

Claims (9)

[Claims] 1. A main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, a memory bus connected to the main storage device, and the plurality of input / output devices. An I / O bus data transfer device for a system comprising a plurality of bridge circuits connecting a plurality of I / O buses to be connected, wherein a read request to the main storage device is transmitted to the plurality of I / O devices by the same data. Output means for outputting, to the main storage device, a broadcast request for requesting the main storage device to transfer data read from the main storage device to each of the plurality of input / output devices; And a plurality of transfer means for transferring data read from the main storage device to the input / output device under its own device when the broadcast request is output. Characteristic input / output bus data transfer device. 2. The input / output bus data transfer device according to claim 1, wherein said output means is provided in a central processing unit connected to said memory bus. 3. The input / output bus data transfer device according to claim 1, wherein said output means is provided in each of said plurality of bridge circuits. 4. A main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, a memory bus connected to the main storage device, and the plurality of input / output devices. An input / output bus data transfer device for a system comprising a plurality of bridge circuits connecting a plurality of input / output buses connected thereto, wherein the data is sent from the input / output device to the memory bus via the bridge circuit. Means for outputting a broadcast request for requesting transfer of data read from the main storage device to each of the plurality of input / output devices based on the read address when the read address is a predetermined specific address, First holding means for holding a read address from the input / output device; and a read address and the broadcast key held by the first holding means. Second holding means for holding one of the addresses of the request, and comparing means for comparing the address added to the data read from the main storage device with the address held in the second holding means. An input / output bus data transfer device, wherein each of the plurality of bridge circuits includes: a data holding unit that holds data read from the main storage device when a match is detected by the comparing unit. 5. A main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, a memory bus connected to the main storage device, and the plurality of input / output devices. An input / output bus data transfer device for a system, comprising: a plurality of bridge circuits connecting a plurality of input / output buses to be connected; and a read address from the input / output device sent via the input / output bus. And a plurality of data read from the main storage device based on the read address when the read address held in the first hold means is a predetermined specific address. Access control means for outputting a broadcast request for requesting transfer to each of the input / output devices; read address held by the first holding means; Second holding means for holding one of the addresses of the request, and comparing means for comparing the address added to the data read from the main storage device with the address held in the second holding means. An input / output bus data transfer device, wherein each of the plurality of bridge circuits includes: a data holding unit that holds data read from the main storage device when a match is detected by the comparing unit. 6. A main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, a memory bus connected to the main storage device, and a plurality of input / output devices. An input / output bus data transfer device for a system including a plurality of bridge circuits connecting a plurality of input / output buses to be connected, wherein the data is sent from the input / output device to the memory bus via the bridge circuit. Means for outputting a broadcast request for requesting transfer of data read from the main storage device to each of the plurality of input / output devices based on the read address when the read address is a predetermined specific address, A first storage unit for sequentially storing read addresses from the input / output device; a read address held in the first storage unit; A second storage unit for sequentially storing one of the addresses of the cast request, and a comparison for comparing an address added to the data read from the main storage device with an address stored in the second storage unit. And an input / output bus data transfer device, wherein each of the plurality of bridge circuits includes means for storing data read from the main storage device when a match is detected by the comparing means. . 7. A main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, a memory bus connected to the main storage device, and the plurality of input / output devices. An input / output bus data transfer device for a system, comprising: a plurality of bridge circuits connecting a plurality of input / output buses to be connected; and a read address from the input / output device sent via the input / output bus. Storage means for sequentially storing data, and when the read address held in the first storage means is a predetermined specific address, the plurality of data read from the main storage device based on the read address are stored. Access control means for outputting a broadcast request for requesting transfer to each of the input / output devices, a read address held in the first storage means, A second storage unit for sequentially storing one of the addresses of the broadcast request; an address added to the data read from the main storage device;
Comparing means for comparing addresses stored in the storage means with each other, and data storage means for sequentially storing data read from the main storage device when a match is detected by the comparing means, each of the plurality of bridge circuits. An input / output bus data transfer device, comprising: 8. A main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, a memory bus connected to the main storage device, and the plurality of input / output devices. An input / output bus data transfer device for a system including a plurality of bridge circuits connecting a plurality of input / output buses to be connected, wherein the data is sent from the input / output device to the memory bus via the bridge circuit. When the identification information for identifying the read request is a specific identification information set in advance, a broadcast request for requesting transfer of data read from the main storage device to each of the plurality of input / output devices based on the identification information is issued. A first holding unit for holding the identification information from the input / output device; and the identification information held by the first holding unit and the broadcaster. Second holding means for holding one of the identification information of the request, and comparing the identification information added to the data read from the main storage device with the identification information held in the second holding means. Input / output bus data transfer, wherein each of the plurality of bridge circuits includes: a comparing unit that performs a read operation; apparatus. 9. A main storage device, a plurality of input / output devices for performing data transfer with the main storage device by direct memory access, a memory bus connected to the main storage device, and the plurality of input / output devices. An I / O bus data transfer device for a system comprising a plurality of bridge circuits connecting a plurality of I / O buses to be connected, wherein a read request from the I / O device sent via the I / O bus A first holding unit for holding identification information for identifying the information, and reading out from the main storage device based on the identification information when the identification information held in the first holding unit is a predetermined specific identification information. Access control means for outputting a broadcast request for requesting transfer of the received data to each of the plurality of input / output devices; identification information held in the first holding means; A second holding unit for holding one of the identification information of the request, and a comparison between the identification information added to the data read from the main storage device and the identification information held in the second holding unit. Input / output bus data transfer, wherein each of the plurality of bridge circuits includes: a comparing unit that performs a read operation; apparatus.