JPS62236061A - Inter-cpu communication system - Google Patents

Abstract

PURPOSE:To obtain a compact data base processing system by using a FIFO as a temporary memory buffer for communication data in a multiprocessor system including plural processors. CONSTITUTION:CPUs 40-43 which perform communication with each other give access to FIFOs 44-47 respectively. These FIFOs 44-47 store temporarily control data and execute or transfer the control data in response to the access of the CPUs 40-43. A signal line 48 secures connection among those FIFOs by a daisy chain system. Thus asynchronous communication is possible among those CPU having different processing times. It is logically possible to realize the communicating among the infinite number of CPUs. In addition, the structures of an additional circuit or software are simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an inter-CPU communication system using a distributed processing system using multiprocessors.

2. Description of the Related Art As a conventional inter-CPU communication method, a CPU communication method in a tightly coupled system shown in FIGS. 3 to 5 is known.

Figure 3 shows random self-access memory (hereinafter referred to as area)
This is an example of a system that uses shared resources to provide interoperability between CPUs. 10 and 11 are CPUs that transfer data, 12
13 is a shared static IIAM 114 to which data to be transferred is accessed; 15 is one C
This is a memory lock signal that prevents other CPUs from operating the semaphore while the PU is operating specific data in the RAM 13, ie, a flag (hereinafter referred to as a semaphore) indicating that a shared resource is being accessed.

The operation of the above configuration will be explained below.

Give CPU 10 a higher priority than CPU II.

After writing the command to be executed by the CPU II and the parameter information for its execution into the shared R5t3, the CPU10 interrupts the CPU11 and starts the command. C
The PU 11 responds to the interrupt, reads the command and input parameters from the shared RAM 13, and executes the specified command. Thereafter, the result is written to the shared RAM 13, and an interrupt is generated to notify the CPU 10 that the command has been completed. With these steps, you can install two CPUs
10 and 11 operate in parallel while dividing the processing. On the other hand, when both CPUs 10 and 11 asynchronously access the shared RAM 13, a semaphore is provided in a specific area of the shared RAM 13 because traffic control for information exchange is required.

In other words, the CPUs 10 and 11 check the semaphore before accessing the shared RAM 13, and if no other CPU is accessing the memory 13, they can make the semaphore busy and then access the shared key "□"'13. returns the semaphore to ready status. On the other hand, when checking the semaphore value so that other CPUs do not change the semaphore value while reading the semaphore on the memory 13 and changing it to busy, the CPU This failure is prevented by outputting the memory lock signal 14 or 15 to the access right arbitration circuit 12.

Figure 4 shows system 1 in which communication between CI) and U is performed using the DMA (=direct memory access) method without using RAM as a shared resource.
It is 1. 20 and 21 are CPUs that perform data transfer.

23 is the I10 port that serves as a path for inputting and outputting control information from the CPU and inputting status information of the data transfer circuit, and 22 is the CP
A data transfer circuit that performs processing such as receiving a transfer request from U, recognizing the other CPU, DMA transfer request, and DMA transfer end interrupt, 24 is a DMA transfer start interrupt signal, 25 and 26 are D
Indicates the MA transfer end interrupt signal.

The operation of the above configuration will be explained below.

C1) When transferring data from U 20 to CPU 21, first CPU 20 transfers I10 to data transfer circuit 22.
Control data containing the destination processor identification code is transferred via the boat 23.

The data transfer circuit 22 looks at the control data and issues a DMA transfer start interrupt 24 to the transfer destination processor. Both the CPU 20 and the CPU 21 to which the interrupt has been applied make preparations for data transfer and then come to a halt state. The data transfer circuit 22 is a CP
After confirming that both U 20 and CPU 21 are in the stopped state, the transfer between memo IJ 1027 and 28 is started.

When the data transfer is finished, CPU 20: CPU 2
DMA transfer end interrupts 25 and 26 are applied to both of the DMA transfer terminals 1 and 1 to bring them out of the stopped state, and post-processing of the data transfer is performed respectively.

Figure 5 shows a GDC (:
graphic display controller) and CPU
It is an interoperable system. 30 is a main CPU that transfers control data including commands and parameters;
31 is a sub CPU that performs screen processing based on the parameters received from the main CPU 30; 32 is a CPU from the CPU 31 to the CPU 30;
File where control data to be transferred to PU 3Q is written
i'o, 33 is CI) FiFo where control data to be transferred from U3Q to CPU 31 is written, 34 is FiFo
Output ead indicating whether data has been input to 33
y signal, 35 is an input Ready signal indicating that the FiFo data is not full, 36 is C after data transfer
This is a termination interrupt that the PU 30 issues to the CPU 31.

After the main CPU 30 writes the control data to the FiFo 33, it issues an end interrupt 36 to the CPU 31 and requests execution of the command in the control data. CPU 31
In response to this interrupt 36, control data is taken out from the FiFo 33 in the order in which it was input. When the execution of the command passed in the control data is completed, the CPU 31 issues an end interrupt 37 to the CPU 30 to notify the CPU 30 of the completion of the command execution.

Data transfer from the CPU 31 to the CPU 30 is similarly performed from File"032ζ2. Therefore, the FiFo
By using the CPU as a shared resource, asynchronous communication can be performed between the CPUs.

The problem that the invention aims to solve However, the above configuration has the following problems.

Although the inter-CPU compatibility with N in Figure 3 as a shared resource and the ability to access any address from both processors is excellent, shared resource management using semaphores is cumbersome, and the accompanying additional circuits It also becomes complicated and requires 3 or more CPs.
It's a problem between U and U.

Communication between CPUs using DMA transfer as shown in Figure 4 and management of shared resources using semaphores become unnecessary, making it possible to connect a large number of CPUs in a star pattern, but the final data transfer circuit is The complexity increases with the number of

As shown in Figure 5, the communication between the CPUs using FiFo simplifies the additional circuitry, and the CPU does not need to manage FiFo information.
In exchange for enabling asynchronous communication between three or more CPs,
There is a drawback that it is difficult to understand between U and U.

The present invention is a method for solving the above-mentioned problems of the prior art.

Means for Solving the Problems In order to solve the above problems, the present invention provides a plurality of FiFo
are connected in a closed loop using a daisy chain method, a plurality of processors are provided on this closed loop in correspondence with each FiFo, control data having a destination processor identification code is transferred from one processor to the closed loop, and this control When the data temporarily remains at Fi[-o, the corresponding processor determines the receiving processor identification code of the control data, executes the command if the control data is addressed to itself, and executes the command if it is not addressed to itself. is transferred to the next processor.

Effect: The above configuration enables asynchronous communication between CPUs with different processing times, and theoretically allows communication between an infinite number of CPUs. Additionally, additional circuits and software for communication become simpler.

EXAMPLES Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the CPU-to-CPU system according to the present invention. 40 to 43 are CPUs that communicate with each other and access FiFos 44, 45, 46, and 47. FiFo 44, 45, 46, 4
7 temporarily stores control data, and CPUs 40 and 41
, 42, 43 to execute or transfer the control data. Reference numeral 48 denotes a signal line that connects each FiFo in a daisy chain manner.

FIG. 2 shows a block configuration of a CPU communication system in a distributed database processing system based on the basic configuration shown in FIG.

50, 51, 52, and 53 are database processing units composed of a CPU, FiFo, etc. The database processing unit 50 is an FiF that receives control data from the CPU 501 and the database processing unit 53.

502, a keyboard 503 for inputting commands and a CRT for displaying input data of the keyboard 503;
It consists of a display 504. The database processing unit 5I has an 1i'iFo for receiving and receiving control data from the CPU 511 and the database processing unit 50.
Consists of 512. The database processing unit 52 is a CP
It consists of a CRT display 523 for displaying screen data sent from the U 521, FiFo 522, and control data from the database processing unit 53. Also, the database processing unit 53 is CI)05
31, a FiFO 532 for receiving and receiving control data from the database processing unit 52, and a hard disk 533 for storing screen data files. 60
indicates a signal line through which control data passes through the FiFo of each unit in a daisy chain format.

Each unit 50 to 53 may be an LSI or a board. Further, the connecting wire 60 between units may be a flat cable, although there is a limit to the length.

From the keyboard 503, the command hard disk 533
20 words of image data are read out and the data is sent to the CPU5.
The operation when inputting "Display on 21" is as follows.

The unit 50 analyzes the command input from the keyboard 503, adds a transfer destination unit number "53", etc. to the command, generates control data, and transfers the command to another unit. Here, since the units are connected in a loop in a daisy chain format, if each FiFo is distributed as shown in Figure 1, each FiFo will always have the CP of the adjacent unit.
U writes control data, reading is done by each FiFo
must be performed by the CPU to which it is connected. Then, the control data from the unit 50 is first written to the FiFo 512 of the adjacent unit 1-51. The unit 51 retrieves the control data written to the FiFo 512 in the order in which they were written, checks the transfer destination unit number therein, and determines whether the data is addressed to itself. Since the control data written to the FiFo 512 has the transfer destination unit number "53", the unit 51 ignores this control data and transfers it to the adjacent unit 5.
Transfer to 2. The unit 52 also performs similar processing. In this way, the control data reaches unit 53. In unit 53, FiF.

Take out the control data written in 532 and send it to yourself.
′. Control ar determines that there are 7, and r7
7p and 7, enter the execution of the rammeter. As a result, 20 words of screen data are read from the hard disk 533.

The read data is appended with the transfer destination unit number "52", added to and edited from the received control data, and sent to the FiF of the adjacent unit 1-50 as new control data.

502. The new control data, like the old control data described above, continues to be transferred until it reaches the target unit 52. When the new control data arrives at the unit 52, it is taken out. Then, the commands in the new control data are immediately executed, and the screen data carried in the new control data is displayed on the CRT 523. If, FiF
If the capacity of o is small and the screen data cannot be carried in one piece of control data, it will be carried in two or more times. Fi
When Fo is full, the output ready signal is
When data is input to o, an input Ready signal is output to each CPU.

As is clear from the above description, according to this embodiment, in the transfer of control data, multiple CPUs do not share one memory, so there is no need for an arbitration circuit for access, and there is no need to specify an address for access. This reduces the need for additional circuitry, while the CPU does not need to know whether the FiF'o is currently being accessed, and there are no complicated communication procedures between units.
High-speed inter-CPU communication is possible with less software.

Effects of the Invention As described above, the present invention provides FiF in a multiprocessor system having a plurality of processors.

By using it as a buffer for temporary storage of communication data, additional circuits for communication and software can be reduced, making it possible to downsize the unit or LSI. A database processing system can be configured. Furthermore, asynchronous communication between a large number of CPUs having different processing times is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main configuration of the CPU-to-CPU system according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the CPU-to-CPU system according to the present invention, and FIGS. Each figure is a block diagram showing a conventional CPU-to-CPU configuration. 40-43, 501, 511, 521, 531
...CPU, 44-47, 502.512,52
2.532---FiFo, 48.60-・Signal line. Name of agent: Patent attorney Toshio Nakao Haka1j1
Figure 1 Figure 2 Figure 37 Figure 5

Claims (1)

[Claims] (1) Multiple first-in first-out buffers connected in a closed loop in a daisy chain manner,
a plurality of processors connected via the buffer on the closed loop, one of the plurality of processors;
Control data having a destination processor identification code transmitted from one processor is placed in the closed loop, and when this control data temporarily remains in the buffer, the corresponding processor determines the destination processor identification code of the control data and controls the control data. An inter-CPU communication method characterized by executing or transferring data.